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EP0233823A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Method for manufacturing a metal insulator semiconductor field effect transistor

Assignee: Fujitsu Ltd
•
Filing: 1987-02-17
•
Granted: —
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Expires: 2007-02-17
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Abstract

Abstract With an increase of integration density in an integrated circuit, the channel length of MIS FET becomes shorter and shorter, which causes a hot carrier effect. To solve this problem, the doping profile of source/drain regions and doping amount must be precisely controlled such that a strong electric field is not generated in a transition region from channel to drain. To obtain this result reflowed sidewalls (14B) of doped silicate glass having a gentle slope are formed on both sides of a gate electrode (13A), and the gate electrode and the sidewalls thus formed are used as a mask for ion implantation. The depth of ion implantation and the doping amount change gradually from the channel region to the drain region avoiding the generation of a strong electric field and thus alleviates the hot carrier effect. The present invention has also an effect of obtaining a passivation layer having a gentle slop on the surface and avoiding broken wire troubles in an aluminium wiring layer formed thereabove.

Inventors

  • 👤 Miura Takao

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-08 21:46
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/0229; H10D30/60; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0144; H10D84/0147; H10P; H10P30/00; H10P30/20; H10P30/22; H10P95/00; Y; Y10; Y10S; Y10S148/00; Y10S148/044; Y10S148/106; Y10S148/157; Y10S148/161; Y10S257/00; Y10S257/90; Y10S257/919; Y10S438/00; Y10S438/965

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 69 words
A method of manufacturing MIS FET, said method comprising the steps of: (a) forming a gate insulating film and a gate electrode on a silicon substrate; (b) forming a sidewall of reflowed insulating material on both sides of said gate electrode; and (c) implanting impurity ions into said substrate to form source and drain regions of said MIS FET using said gate electrode and said sidewalls as a mask.
Claim 2
Independent Claim 69 words
A method of manufacturing MIS FET, said method comprising the steps of: (a) forming a gate insulating film and a gate electrode on a silicon substrate; (b) forming a sidewall of reflowed insulating material on both sides of said gate electrode; and (c) implanting impurity ions into said substrate to form source and drain regions of said MIS FET using said gate electrode and said sidewalls as a mask.
Claim 3
Dependent Claim 77 words
A method of manufacturing MIS FET according to claim 1, wherein said step (b) of forming a sidewall of reflowed insulating material comprises the following sub-steps of: (d) depositing an insulating material on said substrate and said gate electrode; (e) reflowing said insulating material; and (f) etching said reflowed insulating material until the surface of said gate electrode is exposed while a sloped sidewall of said insulating material is left on both sides of the gate electrode.
Claim 4
Dependent Claim 77 words
A method of manufacturing MIS FET according to claim 1, wherein said step (b) of forming a sidewall of reflowed insulating material comprises the following sub-steps of: (g) depositing an insulating material on said substrate and said gate electrode; (h) etching anisotropically said insulating material until the surface of said gate electrode is exposed while a sidewall portion of said insulating material is left on both sides of the gate electrode; and (i) reflowing said insulating material.
Claim 5
Independent Claim 38 words
A method of manufacturing MIS FET according to any one of claims 1, 2 and 3, wherein said insulating material in steps (b), (d), or (g) respectively is a doped silicate glass having a reflow temperature below 1100°C.
Claim 6
Dependent Claim 32 words
A method of manufacturing MIS FET according to claim 4, wherein said silicate glass is doped with an oxide of phosphorus (P) or boron (8) or arsenic (As), or a combination thereof.
Claim 7
Dependent Claim 59 words
A method of manufacturing MIS FET according to claim 2, wherein said etching in step (f) is performed until the surface of said gate electrode is exposed and further the surface edge thereof is partly removed while a sloped sidewall of said insulating material is left on both sides of the gate electrode, thus forming a continuous curved surface.

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