EP0242010A1
Expired / Lapsed
EP
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Clock circuit for a data processor
Assignee: International Business Machines Corp
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Filing: 1987-01-12
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Granted: —
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Expires: 2007-01-12
Abstract
Abstract A clock circuit for supplying a clock signal 62 to a data processor 10 is arranged to supply the clock signal at one of a range of frequencies, under the control of the data processor. The processor can instruct the circuit to supply the clock signal at a maximum frequency to provide maximum data processing capacity or it can instruct it to supply a signal at a selected lower frequency in order to reduce power consumption. The effect of the processor can be overridden by an external event, e.g. an interrupt 20, which forces the clock circuit to produce the clock signal at the maximum frequency in order to minimise the delay in processing the interrupt. The clock circuit includes synchronisation circuitry for ensuring that the clock frequency is changed without generating a glitch.
Inventors
- 👤 Ronald Xavier Arroyo
- 👤 James Thomas Hanna
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-24 08:09
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3234; G06F1/324; G06F1/04; G06F1/08; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
113 words
Clock circuit for clocking a data processor (10) comprising means for producing a clock signal at a first frequency for controlling the data processor during normal operation, characterised in that the clock circuit further comprises : means for producing the clock signal at a second, lower frequency for controlling the data processor outside normal operation, this lower frequency being non-zero, means for changing the clock signal from the first frequency to the second, lower frequency in response to a first indication from the data processor that normal operation is suspended and means for further changing the clock signal to the first frequency in response to a second indication that normal operation is resumed.
Claim 2
Dependent Claim
113 words
Clock circuit for clocking a data processor (10) comprising means for producing a clock signal at a first frequency for controlling the data processor during normal operation, characterised in that the clock circuit further comprises : means for producing the clock signal at a second, lower frequency for controlling the data processor outside normal operation, this lower frequency being non-zero, means for changing the clock signal from the first frequency to the second, lower frequency in response to a first indication from the data processor that normal operation is suspended and means for further changing the clock signal to the first frequency in response to a second indication that normal operation is resumed.
Claim 3
Dependent Claim
31 words
Clock circuit as claimed in claim 1 in which said second,lower frequency is selected from a plurality of frequencies and the first indication further defines the particular frequency to be selected.
Claim 4
Dependent Claim
56 words
Clock circuit as claimed in claim 2 comprising means for producing the clock signal at a third frequency, selected from said plurality of frequencies, and means for changing the clock signal from the second frequency to the third frequency in response to a third indication, the third indication further defining the particular frequency to be selected.
Claim 5
Dependent Claim
22 words
Clock circuit as claimed in claim 2 or claim 3 in which the plurality of frequencies includes a frequency of zero Hertz.
Claim 6
Dependent Claim
31 words
Clock circuit as claimed in claim 2, claim 3 or claim 4 including register means for storing part of each indication, the part stored defining the particular frequency to be selected.
Claim 7
Dependent Claim
20 words
Clock circuit as claimed in any preceding claim arranged to receive such a second indication from the data processor itself.
Claim 8
Dependent Claim
24 words
Clock circuit as claimed in any preceding claim arranged to receive such a second indication in response to an interrupt from external circuit means.
Claim 9
Dependent Claim
70 words
Clock circuit as claimed in any preceding claim in which said means for changing comprises a switch (80) for switching the clock signal from a signal at the first frequency to a signal at the second, lower frequency and further comprises means (68,70,72,74,76,82) for ensuring that, when the clock signal is changed from the first frequency to the second, lower frequency, all these signals are in the same logical state.
Claim 10
Dependent Claim
54 words
Clock circuit as claimed in claim 8 including means for generating an intermediate signal to indicate that the signal at the first frequency and the signal at the second frequency are in the same logical state and means for using this signal to control the time at which the switch (80) may be operated.
References Cited (Backward Citations)
No citation records indexed.
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