EP0242879A2
Expired / Lapsed
EP
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Data processor with wait control allowing high speed access
Assignee: NEC Corp
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Filing: 1987-04-23
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Granted: —
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Expires: 2007-04-23
Abstract
Abstract A slave processor adapted to execute a read/write operation in response to a read/write request signal from a master processor, comprises a first circuit for performing a write operation during a predetermined period of time from the moment a first write request signal is made inactive from an active condition. An second circuit is provided for generating, when another access request signal such as a second write request signal or a read request signal is made active during the above predetermined period of time, an active wait signal requiring the master processor so as to maintain the second access request signal in an active condition. The second circuit also operates to delay an operation indicated by the second access request signal.
Inventors
- 👤 Mitsurou Ohuchi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 01:46
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/17; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3877; G06F9/3879; G06F9/3881
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
118 words
A data processor adapted to execute a read/write operation in response to a read/write request signal from a master processor, comprising first means for performing a write operation during a predetermined period of time from the moment a first write request signal is made inactive from an active condition, and second means for generating, when another access request signal such as a second write request signal or a read request signal is made active during the above predetermined period of time, an active wait signal requiring the master processor so as to maintain the second access request signal in an active condition, the second means also operating to delay an operation indicated by the second access request signal.
Claim 2
Dependent Claim
118 words
A data processor adapted to execute a read/write operation in response to a read/write request signal from a master processor, comprising first means for performing a write operation during a predetermined period of time from the moment a first write request signal is made inactive from an active condition, and second means for generating, when another access request signal such as a second write request signal or a read request signal is made active during the above predetermined period of time, an active wait signal requiring the master processor so as to maintain the second access request signal in an active condition, the second means also operating to delay an operation indicated by the second access request signal.
Claim 3
Dependent Claim
67 words
A processor claimed in Claim 1 wherein the second means includes a read/write controller receiving the read request signal and the write request signal and generating the wait signal only when a read operation is executed and when a read request signal or a write request signal is further inputted during the predetermined period of time from the moment the first write request signal is made inactive.
Claim 4
Dependent Claim
94 words
A processor claimed in Claim 2 further including an internal register, a read data register coupled between the internal register and a data bus so as to temporality hold data read from the internal register, a write data register coupled between the internal register and the bus so as to temporality hold data to be written to the internal register, and an address register coupled between the internal register and an address bus to hold an address of the internal register to be accessed, the above four registers being controlled by the read/write controller.
Claim 5
Dependent Claim
79 words
A processor claimed in Claim 3 wherein the read/write controller responds to a first write request signal so as cause the write data register and the address register to latch information on the data bus and the address bus, respectively, and when a second write request signal is generated before the write operation based on the first write request signal is completed, the read/write controller generates the wait signal without updating the write data register and the address register.
Claim 6
Dependent Claim
73 words
A processor claimed in Claim 3 wherein the read/write controller responds to a first write request signal so as cause the write data register and the address register to latch information on the data bus and the address bus, respectively, and when a read request signal is generated before the write operation based on the first write request signal is completed, the read/write controller generates the wait signal without updating the address register.
References Cited (Backward Citations)
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