EP0248428A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Intermediate frequency amplification circuit capable of detecting a field strength with low electric power
Assignee: NEC Corp
•
Filing: 1987-06-04
•
Granted: —
•
Expires: 2007-06-04
Abstract
Abstract In an intermediate frequency amplification circuit comprising first through n-th differential amplifiers which are connected in cascade to one another with the first amplifier supplied with a circuit input signal and which successively produce amplifier output signals with an n-th amplifier output signal produced as a circuit output signal from the n-th amplifier, first through (n+1)-th rectification circuits are supplied with the respective amplifier output signals with the circuit input signal given to the first rectification circuit. Each rectification circuit comprises a differential unit comprising at least one pair of transistors have different emitter areas from each other to rectify each amplifier output signal and to produce a collector current which is summed up by an adder circuit to be produced as a field strength signal. The rectification circuits may carry out either half-wave rectification or full-wave rectification. A plurality of the above-mentioned pairs may be included in each rectification circuit.
Inventors
- 👤 Katsuji Kimura
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 14:05
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/04; G; G01; G01R; G01R29/00; G01R29/08; G01R29/0864; G01R29/0871; H03F3/45; H03F3/45071; H03G; H03G7/00; H03G7/001
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
351 words
In an intermediate frequency amplification circuit operable in response to a circuit input signal to produce a circuit output signal subjected to amplification, said intermediate frequency amplification circuit comprising first through n-th differential amplifiers which have first through n-th. amplifier input terminal pairs and first through n-th amplifier output terminal pairs, respectively, and which are connected in cascade from said first to said n-th differential amplifiers by successively connecting the amplifier output terminal pair of each differential amplifier to the amplifier input terminal pair of the next following differential amplifier, said circuit input signal being supplied across said first amplifier input terminal pair while said circuit output signal is produced through said n-th amplifier output terminal pair, said intermediate frequency amplification circuit further comprising a measuring circuit responsive to said circuit input signal for measuring a field strength to produce a field strength signal representative of said field strength, the improvement wherein: said measuring circuit comprises: first through (n + 1 )-th differential units which have first through (n+ 1)-th unit input terminal pairs connected to said first through n-th amplifier input terminal pairs and to said n-th amplifier output terminal pair, respectively, and first through (n + 1)-th unit output terminal pairs supplied with first through (n + 1)-th unit output signals, respectively; and an adder circuit connected to said first through (n + 1 )-th- unit output terminal pairs for adding said first through (n + 1)-th unit output signals to one another to produce said field strength signal; each of said first through (n + 1)-th differential units comprising: a primary differential circuit of first and second primary transistors which have first and second base regions, first and second emitter regions, and first and second collector regions, respectively, said first and said second base regions being connected to the amplifier input terminal pair, respectively, while said first and said second emitter regions have an area ratio of 1:k, where k is greater than unity, and are coupled in common to each other, said first and said second collector regions being connected to said unit output terminal pair, respectively.
Claim 2
Dependent Claim
351 words
In an intermediate frequency amplification circuit operable in response to a circuit input signal to produce a circuit output signal subjected to amplification, said intermediate frequency amplification circuit comprising first through n-th differential amplifiers which have first through n-th. amplifier input terminal pairs and first through n-th amplifier output terminal pairs, respectively, and which are connected in cascade from said first to said n-th differential amplifiers by successively connecting the amplifier output terminal pair of each differential amplifier to the amplifier input terminal pair of the next following differential amplifier, said circuit input signal being supplied across said first amplifier input terminal pair while said circuit output signal is produced through said n-th amplifier output terminal pair, said intermediate frequency amplification circuit further comprising a measuring circuit responsive to said circuit input signal for measuring a field strength to produce a field strength signal representative of said field strength, the improvement wherein: said measuring circuit comprises: first through (n + 1 )-th differential units which have first through (n+ 1)-th unit input terminal pairs connected to said first through n-th amplifier input terminal pairs and to said n-th amplifier output terminal pair, respectively, and first through (n + 1)-th unit output terminal pairs supplied with first through (n + 1)-th unit output signals, respectively; and an adder circuit connected to said first through (n + 1 )-th- unit output terminal pairs for adding said first through (n + 1)-th unit output signals to one another to produce said field strength signal; each of said first through (n + 1)-th differential units comprising: a primary differential circuit of first and second primary transistors which have first and second base regions, first and second emitter regions, and first and second collector regions, respectively, said first and said second base regions being connected to the amplifier input terminal pair, respectively, while said first and said second emitter regions have an area ratio of 1:k, where k is greater than unity, and are coupled in common to each other, said first and said second collector regions being connected to said unit output terminal pair, respectively.
Claim 3
Dependent Claim
56 words
An intermediate frequency amplification circuit as claimed in Claim 1, wherein said each differential unit comprises: an additional differential circuit of first and second transistor parts which are differentially connected to each other and which are linked to both of the amplifier input terminal pair of said each differential amplifier and the unit output terminal pair.
Claim 4
Dependent Claim
28 words
An intermediate frequency amplification circuit as claimed in Claim 2, each of said amplifier input terminal pairs consisting of a first and a second amplifier input terminals, wherein;
Claim 5
Dependent Claim
19 words
said first and said second base regions are connected to said first and said second amplifier input terminals, respectively;
Claim 6
Dependent Claim
19 words
said first and said second base regions are connected to said first and said second amplifier input terminals, respectively;
Claim 7
Dependent Claim
5 words
said first transistor part comprising:
Claim 8
Dependent Claim
5 words
said first transistor part comprising:
Claim 9
Dependent Claim
119 words
a first additional transistor which has an emitter region having a predetermined emitter area, a base region connected to said second amplifier input terminal, and a collector region connected in common to the first collector region of said first primary transistor; said second transistor part comprising: a second additional transistor having an emitter region which has an emitter area equal to k-times said predetermined emitter area of said first additional transistor and which is coupled in common to the emitter region of said first additional transistor, said second additional transistor having a base region connected in common to said first base region, and a collector region connected in common to said second collector region of said second primary transistor.
Claim 10
Dependent Claim
119 words
a first additional transistor which has an emitter region having a predetermined emitter area, a base region connected to said second amplifier input terminal, and a collector region connected in common to the first collector region of said first primary transistor; said second transistor part comprising: a second additional transistor having an emitter region which has an emitter area equal to k-times said predetermined emitter area of said first additional transistor and which is coupled in common to the emitter region of said first additional transistor, said second additional transistor having a base region connected in common to said first base region, and a collector region connected in common to said second collector region of said second primary transistor.
Claim 11
Dependent Claim
192 words
An intermediate frequency amplification circuit as claimed in Claim 2, each of said first through n-th amplifier input terminal pairs consisting of first and second amplifier input terminals while each of the unit input terminal pairs consists of first and second unit input terminals, each of the unit output terminal pairs consisting of first and second unit output terminals, wherein: said first transistor part comprises: a plurality of first subsidiary transistors having collector regions connected in common to said first collector region of said first primary transistor, emitter regions having emitter areas substantially equal to that of said first emitter region, and base regions connected in common to said first amplifier input terminal; said second transistor part comprising: a plurality of second subsidiary transistors which equal in number to said first subsidiary transistors and which have collector regions connected in common to the second collector region of said second primary transistor, base regions connected in common to the second base region of said second primary transistor, and emitter regions having emitter areas substantially equal to that of said second emitter region and coupled to the emitter regions of said first subsidiary transistors.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.