Microcomputer

Claim 2

A microprocessor comprising: (a) first means (18) for generating address signals on an address bus (2); and (b) second means (17) for generating address information on an address information line (3), wherein the address information indicates whether or not at least some of the address signals generated now are equal to at least some of the address signals generated previously.

Claim 3

The microprocessor of claim 1, further comprising: (c) third means (34, 35) for storing the address signals generated previously.

Claim 4

The microprocessor according to claim 1 or 2, wherein said second means (17) includes means (40, 41) for comparing parts of both the address signals, and means (42) for generating the address information in response to an output of the comparison means (40, 41).

Claim 5

The microprocessor of claim 3, wherein each of the parts of both the address signals to be compared by said comparison means (40, 41) of said second means (17) consists of higher bits of the corresponding address signals.

Claim 6

The microprocessor of claim 4, wherein said comparison means of said second means includes means (36...39) for masking lower bits of each of both the address signals.

Claim 7

The microprocessor of any of claims l to 5, wherein a signal amplitude of the address information has a value smaller than a signal amplitude of the address signals.

Claim 8

A memory management unit which generates physical address signals for accessing a predetermined address of memory means (7) in response to logical address signals generated by a microprocessor (1), comprising: (a) first means (53) for detecting whether or not at least some of the logical address signals generated now by said microprocessor (1) are equal to at least some of the logical address signals generated previously by said microprocessor (1); and (b) second means (54, 55) for storing the physical address signals corresponding to the logical address signals generated previously by said microprocessor (1), wherein the physical address signals stored in said second means (54, 55) are read out when it has been detected by said first means (53) that both the logical address signals are partly equal.

Claim 9

A memory management unit which generates physical address signals for accessing a predetermined address of memory means (7) in response to logical address signals generated by a microprocessor (1), comprising: (a) first means (53) for detecting whether or not at least some of the logical address signals generated now by said microprocessor (1) are equal to at least some of the logical address signals generated previously by said microprocessor (1); and (b) second means (54, 55) for storing the physical address signals corresponding to the logical address signals generated previously by said microprocessor (1), wherein the physical address signals stored in said second means (54, 55) are read out when it has been detected by said first means (53) that both the logical address signals are partly equal.

Claim 10

The memory management unit of claim 7, further comprising: (c) third means (56) for selectively reading out either of the physical address signals stored in said second means (54, 55) and the physical address signals corresponding to the logical address signals generated now by said microprocessor (1), in response to the detection output of said first means (53).

Claim 11

The memory management unit of claim 7 or 8, wherein said some of the logical address signals to be detected by said first means (53) are higher bits of the logical address signals.

Claim 12

A microcomputer comprising: (a) a microprocessor (1) which includes first means (18) for generating logical address signals on an address bus (2), and second means (17) for generating address information on an address information line (3), the address information indica­ting that at least some of the logical address signals generated now are equal to at least some of the logical address signals generated previously; (b) memory means (7) for storing data for said micropro­cessor (1); and (c) a memory management unit (4) which is connected between said microprocessor (1) and said memory means (7), and which generates physical address signals for accessing a pre­determined address of said memory means (7) in response to the logical address signals generated by said microprocessor (1), wherein said memory management unit (4) further includes means (54, 55) for storing the physical address signals corresponding to the logical address signals generated pre­viously by said microprocessor (1), and wherein the physical address signals stored in the storage means (54, 55) of said memory management unit (4) are read out when it has been de­tected by said second means (17) of said microprocessor (1) that both the logical address signals are partly equal.

Claim 13

A microcomputer comprising: (a) a microprocessor (1) which includes first means (18) for generating logical address signals on an address bus (2), and second means (17) for generating address information on an address information line (3), the address information indica­ting that at least some of the logical address signals generated now are equal to at least some of the logical address signals generated previously; (b) memory means (7) for storing data for said micropro­cessor (1); and (c) a memory management unit (4) which is connected between said microprocessor (1) and said memory means (7), and which generates physical address signals for accessing a pre­determined address of said memory means (7) in response to the logical address signals generated by said microprocessor (1), wherein said memory management unit (4) further includes means (54, 55) for storing the physical address signals corresponding to the logical address signals generated pre­viously by said microprocessor (1), and wherein the physical address signals stored in the storage means (54, 55) of said memory management unit (4) are read out when it has been de­tected by said second means (17) of said microprocessor (1) that both the logical address signals are partly equal.

Claim 14

The microcomputer of claim 10, wherein said memory management means (4) further includes selection means (56) for selectively reading out either of the physical address signals stored in said storage means (54, 55) and the physical address signals corresponding to the logical address signals generated now by said microprocessor (1), in response to the output of said second means (17) of said microprocessor (1).

Claim 15

The microcomputer of claim 10 or 11, wherein said some of the logical address signals to be detected by said second means (17) of said microprocessor (1) are higher bits of the logical address signals.