EP0253530A2
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EP
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Dynamically reconfigurable array logic
Assignee: Honeywell Inc
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Filing: 1987-06-25
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Granted: —
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Expires: 2007-06-25
Abstract
Abstract A dynamically reconfigurable array logic (DRAL) (l0) is capable of in-system logical reconfiguration in real time and comprises a RAM programmable logic array of bits (l2), each bit comprising a fuse connection between logic elements. I/O means (l4) are coupled to the RAM programmable logic array (l2) for logical selection of registered output. A first register (l6) is coupled for receiving data and high-level commands. A sequencer (l8) includes a pair of up/down counters and functions to generate addresses. A timing device (20) controls DMA transfers and issues READ and WRITE strobes. A second register (26) monitors outputs and functions as a comparator, in a first mode, and functions to load outputs during specified time intervals in a second mode.
Inventors
- 👤 Mathew W. Henry
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 04:22
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/17752; H03K19/17704; H03K19/1776
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
122 words
A dynamically reconfigurable array logic characterised in that it comprises: a RAM programmable logic array (l2) comprising an array of bits, each bit comprising a fuse connection between logic elements; I/O means (l4) coupled to the RAM programmable logic array (l2) for logical selection of registered output; first register means (l6) coupled to the RAM programmable logic array (l2) for receiving data and high level commands; sequencer means (l8) coupled to the RAM programmable logic array (l2) for generating addresses; timing means (20) coupled to the RAM programmable logic array (l2) for issuing READ and WRITE strobes; and second register means (26) coupled to the RAM programmable logic array (l2) for monitoring outputs in both a first mode and a second mode;
Claim 2
Dependent Claim
122 words
A dynamically reconfigurable array logic characterised in that it comprises: a RAM programmable logic array (l2) comprising an array of bits, each bit comprising a fuse connection between logic elements; I/O means (l4) coupled to the RAM programmable logic array (l2) for logical selection of registered output; first register means (l6) coupled to the RAM programmable logic array (l2) for receiving data and high level commands; sequencer means (l8) coupled to the RAM programmable logic array (l2) for generating addresses; timing means (20) coupled to the RAM programmable logic array (l2) for issuing READ and WRITE strobes; and second register means (26) coupled to the RAM programmable logic array (l2) for monitoring outputs in both a first mode and a second mode;
Claim 3
Dependent Claim
18 words
Array logic according to claim l, characterised in that the sequencer means includes a pair of up/down counters.
Claim 4
Dependent Claim
18 words
Array logic according to claim l or 2, characterised in that the timing means (20) controls DMA transfers.
Claim 5
Dependent Claim
21 words
Array logic according to any of the preceding claims, characterised in that the second register means includes an interrupt/test register (26).
Claim 6
Dependent Claim
27 words
Array logic of claim 2, characterised in that during the first mode, the second register means (26) loads addresses into the counters of the sequencer means (l8).
Claim 7
Dependent Claim
133 words
A dynamically reconfigurable array logic characterised in that it comprises: a RAM programmable logic array (l2) comprising an array of bits, each bit comprising a fuse connection between logic elements; I/O means (l4) coupled to the RAM programmable logic array for logical selection of a registered output; first register means (l6) coupled to the RAM programmable logic array (l2) for receiving data and high level commands; a pair of up/down counters (l8) coupled to the RAM programmable logic array (l2); timing means (20) coupled to the RAM programmable logic array (l2) for issuing READ and WRITE strobes; and second register means (26) coupled to the RAM programmable logic array (l2) for functioning as a comparator in a first mode and for functioning to load outputs during specified time intervals in a second mode.
Claim 8
Dependent Claim
133 words
A dynamically reconfigurable array logic characterised in that it comprises: a RAM programmable logic array (l2) comprising an array of bits, each bit comprising a fuse connection between logic elements; I/O means (l4) coupled to the RAM programmable logic array for logical selection of a registered output; first register means (l6) coupled to the RAM programmable logic array (l2) for receiving data and high level commands; a pair of up/down counters (l8) coupled to the RAM programmable logic array (l2); timing means (20) coupled to the RAM programmable logic array (l2) for issuing READ and WRITE strobes; and second register means (26) coupled to the RAM programmable logic array (l2) for functioning as a comparator in a first mode and for functioning to load outputs during specified time intervals in a second mode.
Claim 9
Dependent Claim
24 words
Array logic according to claim 6, characterised in that, during the first mode, the second register means (26) loads addresses into the counters (l8).
Claim 10
Dependent Claim
18 words
Array logic according to claim 6 or 7, characterised in that the timing means (20) controls DMA transfers.
Claim 11
Dependent Claim
20 words
Array logic according to any of claims 6 to 8, characterised in that the second register means (26) monitors output.
Claim 12
Dependent Claim
148 words
l0. A dynamically reconfigurable array logic characterised in that it comprises: a RAM programmable logic array (l2) comprisng an array of bits, each bit comprising a fuse connection between logic elements; I/O means (l4) coupled to the RAM programmable logic array (l2) for logical selection of registered output; first register means (l6) coupled to the RAM programmable logic array (l2) for receiving data and high-level commands; sequencer means (l8), including a pair of up/down counters, coupled to the RAM programmable logic array (l2) for generating addresses; timing means (20) coupled to the RAM programmable logic array (l2) for controlling DMA transfers and for issuing READ and WRITE strobes; and second register means (26) coupled to the RAM programmable logic array (l2) for monitoring outputs and for functioning as a comparator in a first mode and for functioning to load outputs during specified time intervals in a second mode.
Claim 13
Dependent Claim
148 words
l0. A dynamically reconfigurable array logic characterised in that it comprises: a RAM programmable logic array (l2) comprisng an array of bits, each bit comprising a fuse connection between logic elements; I/O means (l4) coupled to the RAM programmable logic array (l2) for logical selection of registered output; first register means (l6) coupled to the RAM programmable logic array (l2) for receiving data and high-level commands; sequencer means (l8), including a pair of up/down counters, coupled to the RAM programmable logic array (l2) for generating addresses; timing means (20) coupled to the RAM programmable logic array (l2) for controlling DMA transfers and for issuing READ and WRITE strobes; and second register means (26) coupled to the RAM programmable logic array (l2) for monitoring outputs and for functioning as a comparator in a first mode and for functioning to load outputs during specified time intervals in a second mode.
Claim 14
Dependent Claim
27 words
Array logic according to any of the preceding claims, characterised in that the RAM programmable logic array (l2) is coupled to tri-state latches (28) and transceivers (30).
Claim 15
Dependent Claim
36 words
Array logic according to claim ll, characterised in that the RAM programmable logic array (l2) is coupled to a PROM (32) and a RAM (34) via a local data bus (38) and local address bus (36).
References Cited (Backward Citations)
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