Dynamic semiconductor memory with improved sensing scheme

Claim 2

A dynamic memory device comprising a pair of first digit lines, a pair of second digit lines, a plurality of dynamic type memory cells coupled to said first and second digit lines, a first sense amplifier having a pair of sense nodes, a second sense amplifier having a pair of sense nodes, a pair of first switches coupled between the pair of sense nodes of said first sense amplifier and the pair of sense nodes of said second sense amplifier, a pair of second switches coupled between said pair of first digit lines and the pair of sense nodes of said first sense amplifier, a pair of third switches coupled between said pair of second digit lines and the pair of the sense nodes of said second sense amplifier, a first control circuit for rendering said pair of first switches conductive in an active mode for allowing access to a selected memory cell and non-conductive in a refresh mode, respectively, and a second control circuit for rendering one of said pair of second switches and said pair of third switches conductive in accordance with address information in said active mode and for rendering both of said pair of second switches and said pair of third switches conductive in said refresh mode.

Claim 3

The memory device according to claim 1, in which each of said memory cells includes a storage capacitor and a transfer transistor coupled between said storage capacitor and one of said digit lines.

Claim 4

The memory device according to claim 1, in which each of said sense amplifiers includes a pair of transistors having gates and drains cross-connected at the sense nodes and commonly connected sources.

Claim 5

The memory device according to claim 1, in which said pair of first digit lines are arranged in a first array region and said pair of second digit lines are arranged in a second array region apart from said first array region.

Claim 6

The memory device according to claim 1, in which the memory cells coupled to said pair of first digit lines are connected to a plurality of first word lines and the memory cells coupled to said pair of second digit lines are coupled to a plurality of second word lines, one of said first and second word lines being selected in said active mode and one of said first word lines and one of said second word lines being selected simultaneously in said refresh mode.

Claim 7

A dynamic memory device comprising a pair of first digit lines, a plurality of first word lines, a plurality of first memory cells coupled to said first digit lines and said first word lines, a pair of second digit lines, a plurality of second word lines, a plurality of second memory cells coupled to said second digit lines and said second word lines, a first sense amplifier having a pair of sense nodes, a second sense amplifier having a pair of sense nodes, first connection means for operatively connecting the sense nodes of said first sense amplifier and the sense nodes of said second sense amplifier in parallel, second connection means for operatively connecting said pair of first digit lines and the pair of sense nodes of said first sense amplifier, third connection means for operatively connecting said pair of second digit lines and the pair of sense nodes of said second sense amplifier, word selection means coupled to said first and second word lines for selecting one of said first and second word lines in an access mode and selecting the respective ones of said first and second word lines in a refresh mode, first control means for enabling said first switches in said access mode and dis- enabling said first switches in said refresh mode, respectively, and second control means for enabling either pair of said second and third switches in said access mode and enabling both said second and third switches in said refresh mode.

Claim 8

A dynamic memory device comprising a pair of first digit lines, a plurality of first word lines, a plurality of first memory cells coupled to said first digit lines and said first word lines, a pair of second digit lines, a plurality of second word lines, a plurality of second memory cells coupled to said second digit lines and said second word lines, a first sense amplifier having a pair of sense nodes, a second sense amplifier having a pair of sense nodes, first connection means for operatively connecting the sense nodes of said first sense amplifier and the sense nodes of said second sense amplifier in parallel, second connection means for operatively connecting said pair of first digit lines and the pair of sense nodes of said first sense amplifier, third connection means for operatively connecting said pair of second digit lines and the pair of sense nodes of said second sense amplifier, word selection means coupled to said first and second word lines for selecting one of said first and second word lines in an access mode and selecting the respective ones of said first and second word lines in a refresh mode, first control means for enabling said first switches in said access mode and dis- enabling said first switches in said refresh mode, respectively, and second control means for enabling either pair of said second and third switches in said access mode and enabling both said second and third switches in said refresh mode.