EP0267612A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Timer/counter using a register block
Assignee: NEC Corp
•
Filing: 1987-11-12
•
Granted: —
•
Expires: 2007-11-12
Abstract
Abstract A timer/counter comprising an operation controller coupled to receive a control information for generating control signals for a selected operation, and a register block coupled to a bus and including a plurality of count registers, a corresponding number of timer registers storing various set values and a buffer circuit controlled by the operation controller to sequentially read data from one of the count registers to the bus and then write the data on the bus to the same count register. An incrementer is coupled to the bus and controlled by the operation controller to increment the data on the bus and to ouput an incremented data to the bus. A coincidence flag coupled to the register block is set when the incremented data in a count register of the timer block has coincided with a value stored in a corresponding timer register. A clear controller coupled to the coincidence flag clears the count register having the count value in coincidence with the value of the corresponding timer register.
Inventors
- 👤 Ikuko C/O Nec Corporation Akita
- 👤 Mineo C/O Nec Corporation Akashi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-24 13:40
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812; G06F9/4825; G06F1/00; G06F1/04; G06F1/14
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
170 words
A timer/counter comprising an operation controller coupled to receive a control information for generating control signals for a selected operation, a register block coupled to a bus and including a plurality of count registers, a corresponding number of timer registers storing various set values and a buffer circuit controlled by the operation controller to sequentially read data from one of the count registers to the bus and then write the data on the bus to the same count register, an incrementer coupled to the bus and controlled by the operation controller to increment the data on the bus and to output an incremented data to the bus, a coincidence flag coupled to the register block and set when the incremented data in a count register of the timer block has coincided with a value stored in a corresponding timer register, and a clear controller coupled to the coincidence flag so as to clear the count register having the count value in coincidence with the value of the corresponding timer register.
Claim 2
Dependent Claim
170 words
A timer/counter comprising an operation controller coupled to receive a control information for generating control signals for a selected operation, a register block coupled to a bus and including a plurality of count registers, a corresponding number of timer registers storing various set values and a buffer circuit controlled by the operation controller to sequentially read data from one of the count registers to the bus and then write the data on the bus to the same count register, an incrementer coupled to the bus and controlled by the operation controller to increment the data on the bus and to output an incremented data to the bus, a coincidence flag coupled to the register block and set when the incremented data in a count register of the timer block has coincided with a value stored in a corresponding timer register, and a clear controller coupled to the coincidence flag so as to clear the count register having the count value in coincidence with the value of the corresponding timer register.
Claim 3
Dependent Claim
30 words
A timer/counter claimed in Claim 1 further including a latch latching the output of the incrementer so as to output the latched data through the bus to the register block.
Claim 4
Dependent Claim
65 words
A timer/counter claimed in Claim 1 wherein the register block and the incrementer are controlled so as to sequentially and cyclicly execute on the respective count registers such an operation that the content of one count register is read out to the incrementer where it is incremented in response to a count clock, and then an incremented data is written into the same count register.
Claim 5
Dependent Claim
43 words
A timer/counter claimed in Claim 3 wherein each of the timer register executes an coincidence detection between the set value and the content of a corresponding count register each time the corresponding count register is rewritten with the incremented data from the incrementer.
Claim 6
Dependent Claim
20 words
A timer'counter claimed in Claim 4 wherein each of the timer register includes an array of content addressable memory cells.
Claim 7
Dependent Claim
223 words
A timer / counter claimed in Claim 5 wherein each of the memory cells includes a flipflop having first and second data inputs/outputs receiving a pair of data signals in an inverse phase to each other, a pair of switching transistors respectively connected between the first input / output of the flipflip and a truth data signal input/output and between the second input/output of the flipflop and an inversion data signal input/output, these switching transistors being connected to receive at their control electrodes the same selection signal, and a pair of two-input exclusive OR circuits connected at their respective outputs to a coincidence detection output, one of the exclusive OR circuits being connected at its one input to the truth data signal input/output and at its other input to the second input/output of the flipflip, and the other exclusive OR circuit being connected at its one input to the inversion data signal inputioutput and at its other input to the first input / output of the flipflip, so that when the selection signal is active, the data can be read from and written into the flipflop, and when the selection signal is inactive, the exclusive OR circuits generate at the coincidence detection output a signal indicative of whether or not the input data is the same as the data set in the fifpflop.
Claim 8
Dependent Claim
39 words
A timer/counter claimed in Claim † wherein the register block operates in response to a capture signal so that the incremented data is written not only into one of the count registers but also into a corresponding timer register.
Claim 9
Dependent Claim
125 words
A timer/counter comprising a register block coupled to a bus and including a plurality of count registers, an incrementer coupled to the bus for incrementing the data on the bus and outputting an incremented data to the bus, and means for sequentially generating count stage signals of the same number as that of the count registers in each count cycle, the count stage signals generated in each count cycle being assigned to the count registers, respectively so that there is sequentially executed on the respective count registers such an operation that the content of one count register is read out to the incrementer where it is incremented in response to a count clock, and then an incremented data is written into the same count register.
Claim 10
Dependent Claim
125 words
A timer/counter comprising a register block coupled to a bus and including a plurality of count registers, an incrementer coupled to the bus for incrementing the data on the bus and outputting an incremented data to the bus, and means for sequentially generating count stage signals of the same number as that of the count registers in each count cycle, the count stage signals generated in each count cycle being assigned to the count registers, respectively so that there is sequentially executed on the respective count registers such an operation that the content of one count register is read out to the incrementer where it is incremented in response to a count clock, and then an incremented data is written into the same count register.
Claim 11
Dependent Claim
152 words
A timer/counter comprising a register block coupled to a bus and including a plurality of count registers and a corresponding number of timer registers storing various set values, an incrementer coupled to the bus for incrementing the data on the bus and outputting an incremented data to the bus, and means for sequentially generating count stage signals of the same number as that of the count registers in each count cycle, the count stage signals generated in each count cycle being assigned to the count registers, respectively so that there is sequentially executed on the respective count registers and corresponding timer registers such an operation that the content of one count register is read out to the incrementer where it is incremented in response to a count clock, and then an incremented data is written into the same count register, and is compared with the set value in the corresponding timer register.
Claim 12
Dependent Claim
152 words
A timer/counter comprising a register block coupled to a bus and including a plurality of count registers and a corresponding number of timer registers storing various set values, an incrementer coupled to the bus for incrementing the data on the bus and outputting an incremented data to the bus, and means for sequentially generating count stage signals of the same number as that of the count registers in each count cycle, the count stage signals generated in each count cycle being assigned to the count registers, respectively so that there is sequentially executed on the respective count registers and corresponding timer registers such an operation that the content of one count register is read out to the incrementer where it is incremented in response to a count clock, and then an incremented data is written into the same count register, and is compared with the set value in the corresponding timer register.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.