EP0271412A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
High density ROM in a CMOS gate array
Assignee: Fairchild Semiconductor Corp
•
Filing: 1987-12-09
•
Granted: —
•
Expires: 2007-12-09
Abstract
Abstract A memory circuit implemented in a CMOS array employs both P-channel and N-channel transistors as memory devices. The use of P-channel memory devices is made possible by providing a level-shifting circuit and a voltage reference circuit to compensate for manufacturing process variations and fluctuations in power supply levels. The reference circuit is made up of a series connection of P-channel FETs that are the same as the memory transistors. The reference voltage produced by the reference circuit tracks variations in the power supply and reflects changes in manufacturing processes so that they are compensated in the output of the level shifting circuit. Performance is further enhanced by clocking load FETS that connect the memory transistors to the voltage source, and density is increased by providing two word lines per row of memory transistors.
Inventors
- 👤 Emdadur R. Khan
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 05:54
CPC Classifications
G; G11; G11C; G11C17/00; H; H10; H10D; H10D84/00; H10D84/90; H10D84/903; H10D84/907; G11C17/08; G11C17/10; G11C17/12; H10B; H10B20/00
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
213 words
A memory device for storing information, comprising: a matrix of CMOS FETs for storing information, wherein each FET has a drain, a gate and a source, the gates of the FETs in each row of the matrix are connected to one of a plurality of word-lines, the drains of N-channel FETs in each column of the matrix are connected to one of a plurality of bit-lines, the sources of P-channel FETs in each column of the matrix are also connected to one of the plurality of bit lines, and the stored information is read by sensing voltage levels on the bit-lines; a level-shifting circuit having a first input which is connected to one of the plurality of bit-lines and producing an output related to the voltage level on the bit line; a reference voltage circuit for providing a reference level for the bit-line voltage which compensates for power supply fluctuations and variations in manufacture of the device, said reference circuit comprising a series-connection of a predetermined number of FETs and having an output connected to a second input of said the level-shifting circuit; a sense amplifier connected to the output of said level-shifting circuit for detecting the bit-line voltage levels; and a latch circuit for holding an output voltage from the sense amplifier.
Claim 2
Dependent Claim
213 words
A memory device for storing information, comprising: a matrix of CMOS FETs for storing information, wherein each FET has a drain, a gate and a source, the gates of the FETs in each row of the matrix are connected to one of a plurality of word-lines, the drains of N-channel FETs in each column of the matrix are connected to one of a plurality of bit-lines, the sources of P-channel FETs in each column of the matrix are also connected to one of the plurality of bit lines, and the stored information is read by sensing voltage levels on the bit-lines; a level-shifting circuit having a first input which is connected to one of the plurality of bit-lines and producing an output related to the voltage level on the bit line; a reference voltage circuit for providing a reference level for the bit-line voltage which compensates for power supply fluctuations and variations in manufacture of the device, said reference circuit comprising a series-connection of a predetermined number of FETs and having an output connected to a second input of said the level-shifting circuit; a sense amplifier connected to the output of said level-shifting circuit for detecting the bit-line voltage levels; and a latch circuit for holding an output voltage from the sense amplifier.
Claim 3
Dependent Claim
17 words
The memory device of claim 1 wherein the series connected reference circuit FETs are all P-channel transistors.
Claim 4
Dependent Claim
21 words
The memory device of claim 1 wherein the memory FETs are both P-channel type and N-channel type arranged in a gate-array.
Claim 5
Dependent Claim
41 words
The memory device of claim 1 wherein the predetermined number of FETs in said reference circuit provides a reference voltage level substantially equal to the power supply voltage minus one-half of the difference between the maximum and minimum bit-line voltage levels.
Claim 6
Dependent Claim
144 words
An MOS memory circuit comprising: a matrix arrangement of memory transistors, said memory transistors including P-channel MOS transistors each having its drain electrode connected to a first voltage source, its source electrode connected to a bit line, and its gate electrode connected to a word line; a plurality of load transistors each of which connects a bit line of said memory circuit to a second voltage source, each of said load transistors comprising a P-channel MOS transistor; a reference voltage circuit comprised of a series connection of a plurality of P-channel MOS transistors which produce a reference voltage related to the voltage swing produced on a bit line by actuation of said memory transistors; and means for comparing the voltage on a bit line with said reference voltage and producing an output signal indicative of a binary state represented by a bit line voltage.
Claim 7
Dependent Claim
144 words
An MOS memory circuit comprising: a matrix arrangement of memory transistors, said memory transistors including P-channel MOS transistors each having its drain electrode connected to a first voltage source, its source electrode connected to a bit line, and its gate electrode connected to a word line; a plurality of load transistors each of which connects a bit line of said memory circuit to a second voltage source, each of said load transistors comprising a P-channel MOS transistor; a reference voltage circuit comprised of a series connection of a plurality of P-channel MOS transistors which produce a reference voltage related to the voltage swing produced on a bit line by actuation of said memory transistors; and means for comparing the voltage on a bit line with said reference voltage and producing an output signal indicative of a binary state represented by a bit line voltage.
Claim 8
Dependent Claim
32 words
The memory circuit of claim 5 wherein said comparing means includes a differential amplifier which receives said bit line voltage as one input signal and said reference voltage as another input signal.
Claim 9
Dependent Claim
13 words
The memory circuit of claim 6 wherein said differential amplifier comprises N-channel transistors.
Claim 10
Dependent Claim
25 words
The memory circuit of claim 6 wherein said differential amplifier produces an output signal which comprises the bit line voltage shifted by a predetermined amount.
Claim 11
Dependent Claim
38 words
The memory circuit of claim 5 wherein said load transistors have a predetermined bias voltage applied to their gate electrodes and said series connected transistors of said reference circuit have said bias voltage applied to their gate electrodes.
Claim 12
Dependent Claim
20 words
The memory circuit of claim 9 wherein said bias voltage is equal to the voltage of said first voltage source.
Claim 13
Dependent Claim
53 words
The memory circuit of claim 5 wherein all of the P-channel MOS transistors which comprise said memory transistors, said load transistors and said series-connected reference circuit transistors are formed with the same dimensions so that they have substantially similar properties and thus reduce adverse effects associated with manufacturing process and voltage supply variations.
Claim 14
Dependent Claim
39 words
The memory circuit of claim 5 further including means for reducing the conductivity of said load transistors during the time that a voltage on a word line is varied to actuate the memory transistors whole gates are connected thereto.
Claim 15
Dependent Claim
144 words
An MOS memory circuit, comprising: a matrix arrangement of memory transistors, said memory transistors including P-channel MOS transistors each having its drain electrode connected to a first voltage source, its source electrode connected to one of a plurality of word lines; a plurality of load transistors respectively connecting the bit lines of said memory circuit to a second voltage source, each of said load transistors comprising a P-channel MOS transistor; means for selectively varying the voltage on one of said word lines to actuate the memory transistors whose gates are connected to said one word line; means for reducing the conductivity of said load transistors in coordination with the variation of the voltage on a word line; and means for sensing the voltage of said bit lines when the voltage on a word line is varied to thereby determine information stored in the memory.
Claim 16
Dependent Claim
144 words
An MOS memory circuit, comprising: a matrix arrangement of memory transistors, said memory transistors including P-channel MOS transistors each having its drain electrode connected to a first voltage source, its source electrode connected to one of a plurality of word lines; a plurality of load transistors respectively connecting the bit lines of said memory circuit to a second voltage source, each of said load transistors comprising a P-channel MOS transistor; means for selectively varying the voltage on one of said word lines to actuate the memory transistors whose gates are connected to said one word line; means for reducing the conductivity of said load transistors in coordination with the variation of the voltage on a word line; and means for sensing the voltage of said bit lines when the voltage on a word line is varied to thereby determine information stored in the memory.
Claim 17
Dependent Claim
31 words
The memory circuit of claim 13 wherein said reducing means turns said load transistors off while the voltage on a word line is being varied to read information from the memory.
Claim 18
Dependent Claim
100 words
An MOS memory circuit, comprising: a multiplicity of MOS transistors arranged on a chip in a plurality of rows and a plurality of columns; a plurality of word lines associated with the rows of transistors, there being two word lines per row of transistors, said two word lines being selectively connected to the gates of the transistors in the row in an alternating fashion; and a plurality of bit lines associated with the columns of transistors, each bit line being connected to two transistors in a row whose gates are respectively connected to the two word lines for that row.
Claim 19
Dependent Claim
100 words
An MOS memory circuit, comprising: a multiplicity of MOS transistors arranged on a chip in a plurality of rows and a plurality of columns; a plurality of word lines associated with the rows of transistors, there being two word lines per row of transistors, said two word lines being selectively connected to the gates of the transistors in the row in an alternating fashion; and a plurality of bit lines associated with the columns of transistors, each bit line being connected to two transistors in a row whose gates are respectively connected to the two word lines for that row.
Claim 20
Dependent Claim
24 words
The memory circuit of claim 15 wherein some of said rows of transistors comprise P-channel transistor and other rows of transistors comprise N-channel transistors.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.