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EP0272869A2
Expired / Lapsed
EP
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Dual port type semiconductor memory device realizing a high speed read operation
Assignee: Fujitsu Ltd
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Filing: 1987-12-15
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Granted: —
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Expires: 2007-12-15
Abstract
Abstract In a dual port type semiconductor memory device such as a FIFO, a register (12) is provided between a read side of a memory cell array (1) and a data output (D ou t). When data is read from the memory cell array (1) to the data output (D ou t), a content stored in the memory cell array is transmitted in advance by a preceding read instruction clock to the register (12), thereby enhancing the read operation speed.
Inventors
- 👤 Keizo Aoyama
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 12:37
CPC Classifications
G; G11; G11C; G11C7/00; G06; G06F; G06F5/00; G06F5/06; G06F5/10; G11C8/00; G11C8/16
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
166 words
A semiconductor memory device comprising: a dual port storing portion (1) to which addresses 0,1, ..., and n-1 are allocated; write pointer means (7, 2-W, 3-W, 4-W, 5-W) which is reset by a write reset signal (RST(W)) and counts a write clock signal (W) after receiving said write reset signal, said write pointer means writing input data (Din) into an address location of said storing portion corresponding to the count value of said clock signal; read pointer means (9, 2-R, 3-R, 4-R) which is reset by a read reset signal (RST(R)) and counts a read clock signal (R) as well as said read reset signal after the reception thereof, said read pointer means reading data stored in an address location of said storing means corresponding to the count value of said read clock signal; and a register (12) for storing data read by said read pointer means and transmitting said stored data as output data (D ou t) in response to each read clock signal (R).
Claim 2
Dependent Claim
166 words
A semiconductor memory device comprising: a dual port storing portion (1) to which addresses 0,1, ..., and n-1 are allocated; write pointer means (7, 2-W, 3-W, 4-W, 5-W) which is reset by a write reset signal (RST(W)) and counts a write clock signal (W) after receiving said write reset signal, said write pointer means writing input data (Din) into an address location of said storing portion corresponding to the count value of said clock signal; read pointer means (9, 2-R, 3-R, 4-R) which is reset by a read reset signal (RST(R)) and counts a read clock signal (R) as well as said read reset signal after the reception thereof, said read pointer means reading data stored in an address location of said storing means corresponding to the count value of said read clock signal; and a register (12) for storing data read by said read pointer means and transmitting said stored data as output data (D ou t) in response to each read clock signal (R).
Claim 3
Dependent Claim
60 words
A device as set forth in claim 1, wherein said read pointer means reads data stored in the 0 address of said storing means when said read pointer means receives said read reset signal, and said register stores data read by said read pointer means and transmits said stored data as output data in response to said read reset signal.
Claim 4
Dependent Claim
104 words
A device as set forth in claim 1 or 2, further comprising: an empty detection circuit (16), connected to said write pointer means, for detecting a data-empty state in said storing means, said empty detection circuit receiving said read reset signal and said read clock signal; and a switch circuit (17), connected to said read pointer means, to said register, and to said empty detection circuit, for transmitting input data directly to said register when a data-empty state is detected in said storing means, and transmitting data read by said read pointer means when a data-empty state is not detected in said storing means.
Claim 5
Dependent Claim
101 words
A device as set forth in claim 3, wherein said empty detection circuit comprises: a counter means (162) for counting pulses of said read clock signal, said counter means being reset by said read reset signal; and comparing means (EXo , EX 1 , ..., EX N - 1 , G 4 ), connected to said counter means and to said write pointer means, for comparing the output of said counter means with the output of said write pointer means, thereby detecting said data-empty state when the output of said counter means coincides with the output of said write pointer means.
Claim 6
Independent Claim
16 words
A device as set forth in any preceding claim, wherein said device comprises an FIFO memory.
References Cited (Backward Citations)
No citation records indexed.
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