Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
63 words
A digital filter circuit comprising a plurality of digital filters (11, 12 ...) cascaded to each other between an input (I) and an output terminal (0), each of said digital filters operating at mutually different clock frequencies (fc₁, fc₂...), said frequencies being selected so that the least common multiple thereof is equal to a high-frequency representing the upper end of a desired passband.
Claim 2
Dependent Claim
63 words
A digital filter circuit comprising a plurality of digital filters (11, 12 ...) cascaded to each other between an input (I) and an output terminal (0), each of said digital filters operating at mutually different clock frequencies (fc₁, fc₂...), said frequencies being selected so that the least common multiple thereof is equal to a high-frequency representing the upper end of a desired passband.
Claim 3
Dependent Claim
107 words
A digital filter circuit as in claim 1, wherein each of said digital filters (11, 12) includes a buffer memory (21), a plurality of delay circuits (22, 23, 24, 25, 26) connected in series to said buffer memory (21), first adding means (27, 28, 29) for adding outputs of said delay circuits, coefficient means (32, 33, 34) for multiplying outputs of said adding means (27, 28, 29) by predetermined coefficients, and second adding means (30, 31), for adding outputs of said coefficient means (32, 33, 34),the output of said second adding means (30, 31) being supplied as an input to the next cascaded digital filter (11, 12).
Claim 4
Dependent Claim
46 words
A digital filter circuit as in claim 2, wherein the clock frequency for each respective digital filter (11, 12) is applied to the buffer memory (21) of each respective digital filter (11, 12) for reading out an input signal previously stored in the buffer memory (21).
Claim 5
Dependent Claim
22 words
A digital filter circuit as in one of the preceding claims wherein the digital filter (11, 12) is a digital low-pass filter.