EP0278415A2
Expired / Lapsed
EP
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Memory system and related error detection and correction apparatus
Assignee: Bull HN Information Systems Italia SpA
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Filing: 1988-02-05
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Granted: —
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Expires: 2008-02-05
Abstract
Abstract Memory system and related error detection and correction apparatus wherein the memory, independently on its parallelism, is organized in modules having 1 byte parallelism, each module having a section with 5 bit parallelism for storing SEC-DED codes related to the information stored in the module and wherein a fast memory, addressed with the information codes and the related SEC-DED codes read out from a memory module produces in output an information code, corrected as a function of the SEC-DED code, a parity check bit for the corrected information code and further bits indicative of a corrected single error and uncorrectable multiple error.
Inventors
- 👤 Ferruccio Zulian
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 22:55
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1048
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
197 words
1) Memory System and related error detection and correction apparatus comprising a memory module having address inputs and data inputs, for storing at each memory address a first information binary code and a second error detection and correction binary code related to said information, said first and second code being provided as input to said module, and data outputs for reading out from said module at each address, a third and fourth binary code, which, in absence of memory error, coincide with said first and second binary code respectively and a fast memory having address inputs connected to said data outputs and having read out outputs, said fast memory containing an information set such that for each address defined by said third and fourth code provides in output on said read out outputs a fifth and a sixth binary code, said fifth code being coincident with said first code in absence of memory error and in presence of a correctable error, said sixth code being indicative, depending on case, of the absence of memory error, of the presence of a correctable error in said third code or of the presence in said third code of uncorrectable errors.
Claim 2
Dependent Claim
197 words
1) Memory System and related error detection and correction apparatus comprising a memory module having address inputs and data inputs, for storing at each memory address a first information binary code and a second error detection and correction binary code related to said information, said first and second code being provided as input to said module, and data outputs for reading out from said module at each address, a third and fourth binary code, which, in absence of memory error, coincide with said first and second binary code respectively and a fast memory having address inputs connected to said data outputs and having read out outputs, said fast memory containing an information set such that for each address defined by said third and fourth code provides in output on said read out outputs a fifth and a sixth binary code, said fifth code being coincident with said first code in absence of memory error and in presence of a correctable error, said sixth code being indicative, depending on case, of the absence of memory error, of the presence of a correctable error in said third code or of the presence in said third code of uncorrectable errors.
Claim 3
Dependent Claim
156 words
2) Memory system as claimed in claim 1, where the address inputs of said fast memory are further connected to an input channel for receiving said first code and a parity check bit related to said first code, and where a subset of said read out outputs is connected to a subset of data inputs of said memory module and a further address input of said fast memory receives a signal indicative of read/write operation of said module, said fast memory containing an information set such that for each first binary code received as input at the addressing inputs and when said further address input receives said signal indicative of a write operation, said fast memory provides in output on said output subset said second error detection and correction binary code and on an output among the other read out outputs, a binary signal indicative of parity error/no parity error detected on said first binary code.
Claim 4
Dependent Claim
96 words
3) Memory system as claimed in claim 1, wherein said data inputs of said module comprise a first and second input subsets and comprising further: - a data input channel connected to said first subset to provide said first binary code as input to said module and - a second fast memory, having address inputs connected to said input channel and data outputs connected to said second subset, said second fast memory containing information such that for each first binary code received at the address inputs provides in output said second error detection and correction code.
Claim 5
Dependent Claim
104 words
4) Memory system as claimed in claim 2 wherein said second fast memory has a second signal output in addition to said data outputs connected to said second subset and a second address input in addition to the address inputs connected to said input channel for receiving a parity check bit related to said first binary code, said second fast memory containing information such that for each first binary code received at the address inputs provides in output on said second signal output a binary signal indicative of parity error as a function of the parity check bit received at said second address input.
References Cited (Backward Citations)
No citation records indexed.
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