Video adapter with improved data pathing

Claim 2

A video adaptor for connecting a raster display type monitor to a host computer system including an I/O serving data bus, a digital signal processor, a pixel processor and a frame buffer for storing video data to be displayed on the monitor, the frame buffer having all-point-addressable access to M pixels, each having Z-bits of video data, of a row of pixels on the monitor screen which may not be word aligned, in a single memory cycle, the adapter including, in the pixel processor architecture, input means for converting video data in a pixel, pixel slice or plane mode format on the host data bus to a uniform internal format, means for automatically aligning and storing locally, data to be stored in or accessed from the frame buffer which is not aligned along physical word boundaries, means for selectively performing logical or arithmetic operations on video data stored in the pixel processor, and means for reformatting data processed by the pixel processor into a format suitable for presentation to the host system.

Claim 3

An adapter as claimed in Claim 1 wherein the means for aligning comprises Z selectively actuable separate alignment and storage blocks, each the block including at least one storage register having M bit storage locations therein wherein all of the bits comprising a given pixel are always stored in the same location in all of the Z storage registers.

Claim 4

An adapter as claimed in Claim 2 wherein the means for performing logical or arithmetic operations comprises M arithmetic/logic units (COMBs) selectively connectable to the Z storage registers in a plurality of configurations depending on whether the current frame buffer operation requires the writing of a constant at all M pixel locations accessed, a simple bit-blt copy operation, or a bit-blt operation with logic.

Claim 5

An adapter as claimed in Claim 3 including a first and second set of storage registers in each of the Z alignment and storage blocks, each of the registers having M bit storage locations and means for selectively transferring data from the first and second sets of storage registers in each of the Z blocks to the M arithmetic/logic units as first and second inputs.

Claim 6

An adapter as claimed in Claim 4 including three internal buses, the outputs of the Z first sets of storage registers connected to a first bus, the outputs of the Z second sets of storage registers connected to a second bus, the two inputs of the arithmetic/logic unit block selectively connectable to the first and second buses and the outputs of the M arithmetic/logic unit blocks being connected to a third bus.

Claim 7

An adapter as claimed in Claim 5 wherein each of the Z alignment and storage blocks include an M bit barrel shifter actuable when data accessed from or to be stored in the frame buffer is not aligned on a physical word boundary, and means for causing a shift magnitude decoded from the low order bits of the X address in the frame buffer to be used as a shift control signal for the barrel shifters of the origin of the accessed row of pixels.

Claim 8

An adaptor as claimed in Claim 6 wherein each of the M ALUs includes a special antialiasing logic circuit for processing colour antialiasing data which includes means for combining colour and intensity bit fields of a first and second pixel, the logic circuit comprising a first comparator for producing an output if the two colour bit fields are equal, a second comparator for determining if a first of the two intensity signals is greater than the other, the output of the second comparator forming one of two inputs to a XNOR circuit the other input being a binary a MIN/MAX signal, the output of the XNOR forming one input to a two input AND circuit, the other input being the output of the first comparator, the output of the AND circuit controlling the output selection means of a multiplexor whereby the intensity field of the first pixel becomes as the intensity output field of the logic circuit if the output of the AND is true and the intensity field of the second pixel appears as the output field otherwise, and wherein the colour bit field of the first pixel always appears as the colour output of the circuit.

Claim 9

An adapter as claimed in Claim 6 wherein the input means for converting comprises: interface means for converting data on the host data bus from possible data formats including pixel, pixel slice and plane to a standard internal configuration wherein pixels are stored and may be operated on in a fixed predetermined internal format, means for converting data received on the host data bus having a first narrow bandwidth, to a format in which it may be processed internally and transferred to the frame buffer, the format having a substantially wider bandwidth, and an input buffer for receiving video data from the host processor and a pair of multiplexors located in the data path between the input buffer and the inputs of the Z alignment and storage blocks in any unit which selectively reconfigures the data stored in the input buffer in accordance with one of three 'mode select signals' which cause the data on the inputs to the multiplexor to be switched to different output lines and wherein the data width of the inputs to and output from the multiplexors is the same.

Claim 10

An adapter as claimed in Claim 8 wherein the means for reformatting includes a first output multiplexor connected to one of the storage registers via an internal bus having selective means for connecting subsets of the M pixels or subsets of pixel slices to a second output multiplexor and to a plane select mechanism including means for selecting and connecting specified bit plane data to the second output multiplexors and means in the second output multiplexor to selectively gate pixel, pixel slice, or plane data onto the host data bus.

Claim 11

A video adaptor for connecting a raster display type monitor to a host computer system including an I/O bus, a digital signal processor, a pixel processor and a frame buffer for storing video data to be displayed on the monitor, the frame buffer having simultaneous all-point-addressable access to M pixels, each having Z bits of video data, of a row of pixels on the monitor screen which may not be word aligned, in a single memory cycle, including input interface means for converting data on the host data bus from possible data formats including pixel, pixel slice and plane to a standard internal configuration wherein pixels are stored and may be operated on in a fixed predetermined internal format, the input means further including means for converting data received on the host data bus having a first narrow bandwidth, to a format in which it may be processed internally and transferred to the frame buffer, in a format having a substantially wider bandwidth, means for automatically aligning and temporarily storing, data to be stored in or accessed from the frame buffer which is not aligned along physical word boundaries, the means for aligning including Z selectively actuable separate alignment and storage blocks, each the block including a first and second set of storage registers having M bit storage locations in each register wherein all of the bits comprising a given pixel are always stored in the same location in all of the Z storage registers, and means for selectively transferring data from the first and second sets of storage registers in each of the Z blocks to a set of M arithmetic/logic units as first and second inputs, each of the Z alignment and storage blocks further including an M-bit barrel shifter actuable when data accessed from or to be stored in the frame buffer is not aligned on a physical word boundary, and means for causing a shift magnitude decoded from the low order bits of the X address in the frame buffer of the origin of the accessed row of pixels, to be used as a shift control signal for the barrel shifters, means for selectively performing logical or arithmetic operations on selected pixels or pixel planes comprising the set of M arithmetic/logic units (COMBs) selectively connectable to the Z storage resistors in a plurality of configurations depending on whether a current frame buffer operation requires the writing of a constant at all M pixel locations accessed, a simple bit-blt copy operation; or a bit-blt operation with logic, three internal buses, the outputs of the Z first sets of storage registers connected to a first bus, the outputs of the Z second sets of storage registers connected to a second bus, the two input parts of the arithmetic/logic unit block selectively connectable to the first and second buses and the outputs of the M arithmetic/logic unit blocks being connected to a third bus, and means for reformatting data processed by the processor into a format suitable for presentation to the host system.

Claim 12

A video adaptor for connecting a raster display type monitor to a host computer system including an I/O bus, a digital signal processor, a pixel processor and a frame buffer for storing video data to be displayed on the monitor, the frame buffer having simultaneous all-point-addressable access to M pixels, each having Z bits of video data, of a row of pixels on the monitor screen which may not be word aligned, in a single memory cycle, including input interface means for converting data on the host data bus from possible data formats including pixel, pixel slice and plane to a standard internal configuration wherein pixels are stored and may be operated on in a fixed predetermined internal format, the input means further including means for converting data received on the host data bus having a first narrow bandwidth, to a format in which it may be processed internally and transferred to the frame buffer, in a format having a substantially wider bandwidth, means for automatically aligning and temporarily storing, data to be stored in or accessed from the frame buffer which is not aligned along physical word boundaries, the means for aligning including Z selectively actuable separate alignment and storage blocks, each the block including a first and second set of storage registers having M bit storage locations in each register wherein all of the bits comprising a given pixel are always stored in the same location in all of the Z storage registers, and means for selectively transferring data from the first and second sets of storage registers in each of the Z blocks to a set of M arithmetic/logic units as first and second inputs, each of the Z alignment and storage blocks further including an M-bit barrel shifter actuable when data accessed from or to be stored in the frame buffer is not aligned on a physical word boundary, and means for causing a shift magnitude decoded from the low order bits of the X address in the frame buffer of the origin of the accessed row of pixels, to be used as a shift control signal for the barrel shifters, means for selectively performing logical or arithmetic operations on selected pixels or pixel planes comprising the set of M arithmetic/logic units (COMBs) selectively connectable to the Z storage resistors in a plurality of configurations depending on whether a current frame buffer operation requires the writing of a constant at all M pixel locations accessed, a simple bit-blt copy operation; or a bit-blt operation with logic, three internal buses, the outputs of the Z first sets of storage registers connected to a first bus, the outputs of the Z second sets of storage registers connected to a second bus, the two input parts of the arithmetic/logic unit block selectively connectable to the first and second buses and the outputs of the M arithmetic/logic unit blocks being connected to a third bus, and means for reformatting data processed by the processor into a format suitable for presentation to the host system.

Claim 13

11 An adapter as claimed in Claim 10, wherein the input interface means comprising an input buffer for receiving video data from the host processor and a pair of multiplexors located in the data path between the input buffer and the inputs of the Z alignment and storage blocks which selectively reconfigures the data stored in the input buffer in accordance with one of three 'mode select signals' which cause the data on the inputs to the multiplexor's to be switched to different output lines and wherein the data width of the inputs to and output from the multiplexors is the same.

Claim 14

An adapter for interfacing between a host processor and the local frame buffer memory of a raster scan display monitor and including a pixel processor, the pixel processor being adapted to selectively process video data accessed from the frame buffer and/or from the host processor, the frame buffer having the capability of accessing a row of M pixels each having Z bits of video data accessible on an all-point-addressable basis starting at any pixel address on the screen, the pixel processor including; an input interface unit for converting video data received from the host in pixel, pixel slice, or plane format on a narrow bandwidth data bus into a uniform internal format for presentation to the frame buffer and to the logic and storage circuitry in the pixel processor, Z plane channel units for storing and aligning at least M bits of video data the data being selectively received from the input interface unit, the frame buffer, or one or more of M arithmetic/logic units in the pixel processor, the M arithmetic/logic units being actuable to selectively perform both logic and arithmetic operations on video data stored in and selectively accessible from the plane channel units, the output of the M arithmetic/logic being selectively transferred to the plane channel units or to the frame buffer, an internal bus structure interconnecting the Z plane channel units, the M arithmetic/logic units, and an output interface unit, the output interface unit being selectively operable to convert video data stored in the Z plane channel units in the format of Z M bit packets representative of M Z bit pixels to pixel, pixel slice or plane format to a bandwidth and format compatible with the host system.

Claim 15

An adapter for interfacing between a host processor and the local frame buffer memory of a raster scan display monitor and including a pixel processor, the pixel processor being adapted to selectively process video data accessed from the frame buffer and/or from the host processor, the frame buffer having the capability of accessing a row of M pixels each having Z bits of video data accessible on an all-point-addressable basis starting at any pixel address on the screen, the pixel processor including; an input interface unit for converting video data received from the host in pixel, pixel slice, or plane format on a narrow bandwidth data bus into a uniform internal format for presentation to the frame buffer and to the logic and storage circuitry in the pixel processor, Z plane channel units for storing and aligning at least M bits of video data the data being selectively received from the input interface unit, the frame buffer, or one or more of M arithmetic/logic units in the pixel processor, the M arithmetic/logic units being actuable to selectively perform both logic and arithmetic operations on video data stored in and selectively accessible from the plane channel units, the output of the M arithmetic/logic being selectively transferred to the plane channel units or to the frame buffer, an internal bus structure interconnecting the Z plane channel units, the M arithmetic/logic units, and an output interface unit, the output interface unit being selectively operable to convert video data stored in the Z plane channel units in the format of Z M bit packets representative of M Z bit pixels to pixel, pixel slice or plane format to a bandwidth and format compatible with the host system.

Claim 16

An adapter as claimed in Claim 12 wherein each of the Z plane channel units includes, first and second storage register means having their outputs connected to first and second internal busses, an M bit barrel shifter for storing a corresponding bit from M pixels, means for selectively presenting a shift signal to the shifter of a magnitude equal to the offset of a current frame buffer pixel row origin address, from a word boundary in the buffer, the output of the barrel shifter being selectively connectable to the first register means or to the frame buffer data bus, the input of the second storage means being selectively connectable to the output of the first storage means and, means for selectively transferring the contents of the first and second storage means to the M arithmetic/logic units via the first and second buses.