EP0282137A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
EPROM memory cell with two symmetrical half-cells and separate floating gates
Assignee: STMicroelectronics SRL
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Filing: 1988-03-04
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Granted: —
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Expires: 2008-03-04
Abstract
Abstract An EPROM memory cell (C) including a source (S), a drain (D), a floating gate (F) and a control gate (G) with interposed dielectric oxide (02) is made up of two symmetrical half-cells (C1, C2) having the drain (D) and the control gate (G) in common, the sources (S) physically separated but electrically connected with each other and the floating gates (F) separated physically and electrically.
Inventors
- 👤 Giuseppe Corda
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 13:22
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0441; H; H10; H10B; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
69 words
EPROM memory cell including a source (S), a drain (D), a floating gate (F) and a control gate (G) with dielectric oxide (02) placed between said gates (F, G), characterized in that it consists of two symmetrical half-cells (C1, C2 having the drain (D) and the control gate (G) in common, the sources (S) separated physically but connected electrically together and the floating gates (F) separated physically and electrically.
Claim 2
Dependent Claim
69 words
EPROM memory cell including a source (S), a drain (D), a floating gate (F) and a control gate (G) with dielectric oxide (02) placed between said gates (F, G), characterized in that it consists of two symmetrical half-cells (C1, C2 having the drain (D) and the control gate (G) in common, the sources (S) separated physically but connected electrically together and the floating gates (F) separated physically and electrically.
Claim 3
Dependent Claim
112 words
Memory cell in accordance with claim 1 characterized in that it is included in an EPROM memory matrix made up of a plurality of parallel source lines (S) electrically connected together, a plurality of parallel drain lines (D) alternating with said source lines (S), a plurality of parallel control gate lines (G) arranged perpendicularly to said source lines (S) and drain lines (D), floating gate areas (F) placed in the spaces between said source lines (S) and drain lines (D) under said control gate lines (G) and oxide areas (01, 02, 03) alternating with said source lines (S), drain lines (D), and control gate lines (G) and said floating gate areas (F).
Claim 4
Dependent Claim
28 words
Memory cell in accordance with claim 2 characterized in that said source lines (S), drain lines (D) and control gate lines (G) are equally spaced from each other.
References Cited (Backward Citations)
No citation records indexed.
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