Pattern display signal generating apparatus and display apparatus using the same

Claim 2

A pattern display signal generating apparatus, characterized in that the apparatus comprises memory means (26) for storing predetermined pattern data and separately outputting even-numbered bits and odd-numbered bits of the pattern data in parallel when scanned; timing generating means (27) for generating an address for scanning the memory means and generating first and second clock signals having a predetermined phase difference; first shift register means (28) for shifting the odd-numbered bits and outputting the same in series in synchronization with the first clock signal; second shift register means (29) for shifting the even-numbered bits and outputting the same in series in synchronization with the second clock signal; and logical operation means (30, 31, 32) for performing at least one predetermined logical operation between outputs of the first and second shift register means to generate a pattern display signal.

Claim 3

A pattern display signal generating apparatus as claimed in claim 1, characterized in that the first and second clock signals have a phase difference of 180°, and thereby the logical operation means (30, 31, 32) performs the predetermined logical operation between adjacent even-numbered and odd-numbered bits which overlaps with each other on a time axis.

Claim 4

A pattern display signal generating apparatus as claimed in claim 1, characterized in that the predetermined pattern data is data obtained from data related to a contour portion of a corresponding pattern, and in that the predetermined pattern data has a first bit arrangement in which consecutive black dot data having binary ones in each line of the contour pattern data are represented by consecutive dot data having black dot data for every other dot, and a second bit arrangement in which consecutive white dot data having binary zeros inside the contour portion are represented by consecutive black data, and a third bit arrangement in which a change from a white dot datum to a black dot datum is represented as it is.

Claim 5

A pattern display signal generating apparatus as claimed in claim 4, characterized in that the logical operation means is an exclusive-OR circuit (32), and an output signal of the exclusive-OR circuit forms a contour pattern display signal which is used for highlighting the display of the contour of the pattern.

Claim 6

A pattern display signal generating apparatus as claimed in claim 4, characterized in that the logical operation means is an AND circuit (30), and an output signal of the AND circuit forms a display signal for displaying an inner portion of the pattern excluding the contour portion thereof.

Claim 7

A pattern display signal generating apparatus as claimed in claim 1, characterized in that the logical operation means is an OR circuit (31), and an output of the OR circuit forms a display signal for displaying the whole pattern.

Claim 8

A pattern display signal generating apparatus as claimed in claim 1, characterized in that the pattern display signal generating apparatus further comprises display memory means (24) for supplying a character code to the memory means (26) as its address signal, a read/write address supply means (20, 21) for supplying read and write addresses for the display memory means, and an address selecting means (22) for selecting one of the read and write addresses from the read/write address supply means.

Claim 9

A pattern display apparatus comprising control means (50) for designating a character code corresponding to a character pattern to be displayed; pattern signal generating means (100) for generating pattern display signals corresponding to a pattern to be displayed; signal processing means (60) for subjecting the pattern display signals to predetermined signal processings and for generating a corresponding video signal; and display means (70) for displaying a pattern corresponding to the video signal, characterized in that the pattern generating signal generating means (100) comprises display memory means (24) for storing the character code from the control means; memory means (26) for storing predetermined pattern data and separately outputting even-numbered bits and odd-numbered bits of the pattern data in parallel when a pattern data designated by the character code from the display memory means is scanned; timing generating means (27) for generating an address for scanning the memory means and for generating first and second clock signals having a predetermined phase difference; first shift register means (28) for shifting the odd-numbered bits and outputting the same in series in synchronization with the first clock signal; second shift register means (29) for shifting the even-numbered bits and outputting the same in series in synchronization with the second clock signal; and logical operation means (30, 31, 32) for performing a plurality of predetermined logical operations between outputs of the first and second shift register means to generate the pattern display signals to be supplied to the signal processing means.

Claim 10

A pattern display apparatus comprising control means (50) for designating a character code corresponding to a character pattern to be displayed; pattern signal generating means (100) for generating pattern display signals corresponding to a pattern to be displayed; signal processing means (60) for subjecting the pattern display signals to predetermined signal processings and for generating a corresponding video signal; and display means (70) for displaying a pattern corresponding to the video signal, characterized in that the pattern generating signal generating means (100) comprises display memory means (24) for storing the character code from the control means; memory means (26) for storing predetermined pattern data and separately outputting even-numbered bits and odd-numbered bits of the pattern data in parallel when a pattern data designated by the character code from the display memory means is scanned; timing generating means (27) for generating an address for scanning the memory means and for generating first and second clock signals having a predetermined phase difference; first shift register means (28) for shifting the odd-numbered bits and outputting the same in series in synchronization with the first clock signal; second shift register means (29) for shifting the even-numbered bits and outputting the same in series in synchronization with the second clock signal; and logical operation means (30, 31, 32) for performing a plurality of predetermined logical operations between outputs of the first and second shift register means to generate the pattern display signals to be supplied to the signal processing means.

Claim 11

A pattern display apparatus as claimed in claim 8, characterized in that the logical operation means is composed of an AND circuit (30), an OR circuit (31) and an exclusive-OR circuit (32).

Claim 12

A pattern display apparatus as claimed in claim 9, characterized in that the first and second clock signals have a phase difference of 180°, and thereby the logical operation means (30, 31, 32) performs the predetermined logical operations between adjacent even-numbered and odd-numbered bits which overlaps with each other on a time axis.

Claim 13

A pattern display apparatus as claimed in claim 10, characterized in that the predetermined pattern data is data obtained from data related to a contour portion of a corresponding pattern, and in that the predetermined pattern data has a first bit arrangement in which consecutive black dot data having binary ones in each line of the contour pattern data are represented by consecutive dot data having black dot data for every other dot, and a second bit arrangement in which consecutive white dot data having binary zeros inside the contour portion are represented by consecutive black data, and a third bit arrangement in which a change from a white dot datum to a black dot datum is represented as it is, and in that the output signal of the exclusive-OR circuit (32) forms a display signal of the contour portion of the pattern, and in that the signal processing means (60) processes the video signal so that by use of the display signal of the contour portion, the contour portion is highlighted on the picture plane of the display means (70).