Nonvolatile semiconductor memory device

Claim 2

A nonvolatile semiconductor memory device characterized by comprising: a write line layer (WL); a read line layer (RL); a write gate line layer (WG, SG); a control gate line layer (CG); a read gate line layer (RG); a cell transistor (32) formed of a floating gate type MOS transistor, for storing an electric charge, whose gate is connected to said control gate line layer; a first selecting transistor (31) formed of an MOS transistor, whose gate is connected to said read gate line layer, one terminal of whose source-drain path is connected to said read line layer, and the other ter­minal of the source-drain path is connected to one ter­minal of the source-drain path of said cell transistor; and a second selecting transistor (33) formed of an MOS tran-sistor, whose gate is connected to said write gate line layer, one terminal of whose source-drain path is connected to said write line layer, and the other termi­nal of the source-drain path is connected to the other terminal of said source-drain path of said cell tran­sistor.

Claim 3

The memory device according to claim 1, charac­terized in that said write gate line layer (SG) and said read gate line layer (RG) are interconnected with each other to form a selecting gate line.

Claim 4

The memory device according to claim 1, charac­terized in that said read gate line layer (RG) and said control gate line layer (CG) are interconnected with each other to form a common gate line.

Claim 5

The memory device according to claim 1, charac­terized in that said write line layer (WL) applies to said one terminal of said source-drain path of said second selecting transistor a first voltage in the data write mode, and a second voltage lower than said first voltage in the data erase and read modes, said write gate line layer (WG) applies to said gate of said second selecting transistor said first voltage in the data erase and write modes, and a third voltage lower than said first voltage and higher than said second voltage in the read mode, said control gate line layer (CG) applies to said control gate of said cell transistor said first voltage in the data erase mode, and said second voltage in the data write and read modes, said read gate line layer (RG) applies to said gate of said first selecting transistor said second voltage in the data erase and write modes, and said third voltage in the data read mode; and said read line layer (RL) applies said third voltage to said one terminal of said source-drain path of said first selecting transistor in the data read mode.

Claim 6

The memory device according to claim 2, charac­terized in that said write line layer (WL) applies to said one terminal of said source-drain path of said second selecting transistor a first voltage in the data write mode, and a second voltage lower than said first voltage in the data erase and read modes, said selecting gate line layer applies to said gates of said first and second selecting transistors said first voltage in the data erase and write modes, and a third voltage lower than said first voltage and higher than said second voltage in the read mode, said control gate line layer (CG) applies to said control gate of said cell tran­sistor said first voltage in the data erase mode, and said second voltage in the data write and read modes, and said read line layer (RL) applies said third voltage to said one terminal of said source-drain path of said first selecting transistor in the write and data read modes.

Claim 7

The memory device according to claim 3, characterized in that said write line layer (WL) applies to said one terminal of said source-drain path of said second selecting transistor a first voltage in the data write mode, and a second voltage lower than said first voltage in the data erase and read modes, said common gate line layer applies to said gates of said first selecting transistor and said cell transistor said first voltage in the data erase mode, said second voltage in the write mode, and a third voltage lower than said first voltage and higher than said second voltage in the read mode, said write gate line layer (SG) applies to said gate of said second selecting transistor said first voltage in the data erase and write modes, and said third voltage in the data read mode, and said read line layer (RL) applies to said one terminal of said source-drain path of said first selecting transistor said second voltage in the data erase mode, and said third voltage in the data read mode.

Claim 8

The memory device according to claim 1, charac­terized in that said read line layer (RL) is connected to a power source (Vcc) via a load circuit (38), and a signal on the read line layer is supplied to a sense amplifier circuit (35).

Claim 9

The memory device according to claim 7, charac­terized in that said load circuit (38) comprises a MOS transistor (36) which normally turned on.

Claim 10

The memory device according to claim 7, charac­terized in that said load circuit (38) comprises a MOS transistor (36) which is turned on by a clock signal.

Claim 11

The memory device according to claim 9, characterized in that the voltage of said read gate line layer (RG) is supplied to said gate of said first selecting transistor (31) in synchronism with said clock signal.

Claim 12

The memory device according to claim 7, characterized in that said sense amplifier circuit (35) is an inverter circuit.

Claim 13

The memory device according to claim 2, characterized in that said read line layer (RL) is con­nected to a power source (Vcc) via a load circuit (38), and a signal on the read line layer is supplied to a sense amplifier circuit (35).

Claim 14

The memory device according to claim 12, characterized in that said load circuit (38) comprises a MOS transistor (36) which normally turned on.

Claim 15

The memory device according to claim 12, characterized in that said load circuit (38) comprises a MOS transistor (36) which is turned on by a clock signal.

Claim 16

The memory device according to claim 14, characterized in that the voltage of said selecting gate line layer (RG) is supplied to said gates of said first and second selecting transistors (31, 33) in synchronism with said clock signal.

Claim 17

The memory device according to claim 12, characterized in that said sense amplifier circuit (35) is an inverter circuit.

Claim 18

the memory device according to claim 3, characterized in that said read line layer (RL) is con­nected to a power source (Vcc) via a load circuit (38), and a signal on the read line layer is supplied to a sense amplifier circuit (35).

Claim 19

The memory device according to claim 17, characterized in that said load circuit (38) comprises a MOS transistor (35) which normally turned on.

Claim 20

The memory device according to claim 17, characterized in that said load circuit (38) comprises a MOS transistor (36) which is turned on by a clock signal.

Claim 21

The memory device according to claim 19, characterized in that the voltage of said common gate line layer is supplied to said gates of said first and second selecting transistors (31, 33) in synchronism with said clock signal.

Claim 22

The memory device according to claim 17, characterized in that said sense amplifier circuit (35) is an inverter circuit.

Claim 23

A nonvolatile semiconductor memory device characterized by comprising: a semiconductor substrate (10) of a first conduc­tivity type; first to fourth diffusion layers (11, 12, 13, 14) of a second conductivity type formed in said substrate; a first channel region (15) formed between said first and second diffusion layers; a second channel region (18) formed between said second and third diffusion layers; a third channel region (24) formed between said third and fourth diffusion layers; a first gate electrode (17) formed above said first channel region; a floating gate electrode (20) formed above said second channel region, and extending above said third diffusion layer; a control gate electrode (23) formed above said floating gate electrode; a second gate electrode (26) formed above said third channel region; a first insulating layer formed between said second channel region and said floating gate electrode; a second insulating layer formed between said third diffusion layer and said extending portion of said floating gate electrode, the second insulating layer having a thickness thinner than that of said first insulating layer; a write line layer (WL) for supplying a predeter­mined voltage to said fourth diffusion layer in data erase, write, and read modes; a write gate line layer (WG) for supplying a prede­termined voltage to said second gate electrode in the data erase, write, and read modes; a control gate line layer (CG) for supplying a pre­determined voltage to said control gate electrode in the data erase, write, and read modes; a read gate line layer (RG) for supplying a prede­termined voltage to said first gate electrode in data erase, write, and read modes; and a read line layer (RL) for supplying a predeter­mined voltage to said first diffusion layer in the data erase, write, and read modes.

Claim 24

A nonvolatile semiconductor memory device characterized by comprising: a semiconductor substrate (10) of a first conduc­tivity type; first to fourth diffusion layers (11, 12, 13, 14) of a second conductivity type formed in said substrate; a first channel region (15) formed between said first and second diffusion layers; a second channel region (18) formed between said second and third diffusion layers; a third channel region (24) formed between said third and fourth diffusion layers; a first gate electrode (17) formed above said first channel region; a floating gate electrode (20) formed above said second channel region, and extending above said third diffusion layer; a control gate electrode (23) formed above said floating gate electrode; a second gate electrode (26) formed above said third channel region; a first insulating layer formed between said second channel region and said floating gate electrode; a second insulating layer formed between said third diffusion layer and said extending portion of said floating gate electrode, the second insulating layer having a thickness thinner than that of said first insulating layer; a write line layer (WL) for supplying a predeter­mined voltage to said fourth diffusion layer in data erase, write, and read modes; a write gate line layer (WG) for supplying a prede­termined voltage to said second gate electrode in the data erase, write, and read modes; a control gate line layer (CG) for supplying a pre­determined voltage to said control gate electrode in the data erase, write, and read modes; a read gate line layer (RG) for supplying a prede­termined voltage to said first gate electrode in data erase, write, and read modes; and a read line layer (RL) for supplying a predeter­mined voltage to said first diffusion layer in the data erase, write, and read modes.

Claim 25

The memory device according to claim 22, characterized in that said write line layer (WL) applies to said fourth diffusion layer a first voltage in the data write mode, and a second voltage lower than said first voltage in the data erase and read modes, said write gate line layer (WG) applies to said second gate electrode said first voltage in the data erase and write modes, and a third voltage lower than said first voltage and higher than said second voltage in the read mode, said control gate line layer (CG) applies to said control gate electrode said first voltage in the data erase mode, and said second voltage in the data write and read modes, said read gate line layer (RG) applies to said first gate electrode said second voltage in the data erase and write modes, and said third voltage in the data read mode; and said read line layer (RL) applies said third voltage to said first diffusion layer in the data read mode.

Claim 26

The memory device according to claim 22, characterized in that said read line layer (RL) is con­nected to a power source (Vcc) via a load circuit (38), and a signal on the read line layer is supplied to a sense amplifier circuit (35).

Claim 27

The memory device according to claim 24, characterized in that said load circuit (38) comprises a MOS transistor (36) which normally turned on.

Claim 28

The memory device according to claim 24, characterized in that said load circuit (38) comprises a MOS transistor (36) which is turned on by a clock signal.

Claim 29

The memory device according to claim 26, characterized in that the voltage of said read gate line layer (RG) is supplied to said first gate electrode in synchronism with said clock signal.

Claim 30

The memory device according to claim 24, characterized in that said sense amplifier circuit (35) is an inverter circuit.

Claim 31

The memory device according to claim 22, characterized in that said write gate line layer (WG) and said read gate line layer (RG) are interconnected with each other.

Claim 32

The memory device according to claim 22, characterized in that said control gate line layer (CG) and said read gate line layer (RG) are interconnected with each other.

Claim 33

A nonvolatile semiconductor memory device comprising: a semiconductor substrate (10) of a first conduc­tivity type; first to third diffusion layers (11, 13, 14) of a second conductivity type formed in said substrate; first and second channel regions (15, 18) formed in series between said first and second diffusion layers; a third channel region (24) formed between said second and third diffusion layers; a first gate electrode (17) formed above said first channel region; a floating gate electrode (20) formed above said second channel region, and extending above said second diffusion layer; a control gate electrode (23) formed above said floating gate electrode; a second gate electrode (26) formed above said third channel region a first insulating layer formed between said second channel region and said floating gate electrode; a second insulating layer formed between said third diffusion layer and said extending portion of said floating gate electrode, the second insulating layer having a thickness thinner than that of said first insulating layer; a write line layer (WL) for supplying a predeter­mined voltage to said third diffusion layer in data erase, write and read modes; a write gate line layer (WG) for supplying a prede­termined voltage to said second gate electrode in data erase, write and read modes; a control gate line layer (CG) for supplying a pre­determined voltage to said control gate electrode in data erase, write and read modes; a read gate line layer (RG) for supplying a prede­termined voltage to said first gate electrode in data erase, write and read modes; and a read line layer (RL) for supplying a predeter­mined voltage to said first diffusion layer in data erase, write and read modes.

Claim 34

A nonvolatile semiconductor memory device comprising: a semiconductor substrate (10) of a first conduc­tivity type; first to third diffusion layers (11, 13, 14) of a second conductivity type formed in said substrate; first and second channel regions (15, 18) formed in series between said first and second diffusion layers; a third channel region (24) formed between said second and third diffusion layers; a first gate electrode (17) formed above said first channel region; a floating gate electrode (20) formed above said second channel region, and extending above said second diffusion layer; a control gate electrode (23) formed above said floating gate electrode; a second gate electrode (26) formed above said third channel region a first insulating layer formed between said second channel region and said floating gate electrode; a second insulating layer formed between said third diffusion layer and said extending portion of said floating gate electrode, the second insulating layer having a thickness thinner than that of said first insulating layer; a write line layer (WL) for supplying a predeter­mined voltage to said third diffusion layer in data erase, write and read modes; a write gate line layer (WG) for supplying a prede­termined voltage to said second gate electrode in data erase, write and read modes; a control gate line layer (CG) for supplying a pre­determined voltage to said control gate electrode in data erase, write and read modes; a read gate line layer (RG) for supplying a prede­termined voltage to said first gate electrode in data erase, write and read modes; and a read line layer (RL) for supplying a predeter­mined voltage to said first diffusion layer in data erase, write and read modes.

Claim 35

The memory device according to claim 31, characterized in that said write line layer (WL) applies to said third diffusion layer a first voltage in the data write mode, and a second voltage lower than said first voltage in the data erase and read modes, said write gate line layer (WG) applies to said second gate electrode said first voltage in the data erase and write modes, and a third voltage lower than said first voltage and higher than said second voltage in the read mode, said control gate line layer (CG) applies to said control gate electrode said first voltage in the data erase mode, and said second voltage in the data write and read modes, said read gate line layer (RG) applies to said first gate electrode said second voltage in the data erase and write modes, and said third voltage in the data read mode; and said read line layer (RL) applies said third voltage to said first diffusion layer in the data read mode.

Claim 36

The memory device according to claim 31, characterized in that said read line layer (RL) is con­nected to a power source (Vcc) via a load circuit (38), and a signal on the read line layer is supplied to a sense amplifier circuit (35).

Claim 37

The memory device according to claim 33, characterized in that said load circuit (38) comprises a MOS transistor (36) which is normally turned on.

Claim 38

The memory device according to claim 33, characterized in that said load circuit (38) comprises a MOS transistor (36) which is turned on by a clock signal.

Claim 39

The memory device according to claim 35, characterized in that the voltage of said read gate line layer (RG) is supplied to said first gate electrode in synchronism with said clock signal.

Claim 40

The memory device according to claim 33, characterized in that said sense amplifier circuit (35) is an inverter circuit.

Claim 41

The memory device according to claim 31, characterized in that said write gate line layer (WG) and said read gate line layer (RG) are interconnected with each other.

Claim 42

The memory device according to claim 31, characterized in that said control gate line layer (CG) and said read gate line layer (RG) are interconnected with each other.

Claim 43

The memory device according to claim 31, characterized in that said first gate electrode (17) and said control gate electrode (23) are interconnected with each other.