EP0285064A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Multi-chip module structure
Assignee: Hitachi Ltd
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Filing: 1988-03-28
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Granted: —
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Expires: 2008-03-28
Abstract
Abstract In a pin grid array type multi-chip module structure (10) comprised of a ceramic multi-layer wiring board (1) having the top surface on which a plurality of semiconductor devices (2 or 3) are carried, divisional board areas (A or B) each having the same size are respectively allotted to individual semiconductor devices (2 or 3) of the same type. Within respective divisional board areas, the positional relation between the array arrangement of connecting pads on the top surface for connection to the semiconductor devices and the array arrangement of I/O pins (4) on the bottom surface of the board is so determined as to be constant. Metallized patterns inside the board which are to be connected power supply I/O pins (4) and grounding I/0 pins (4) are made constant for respective divisional board areas allotted to individual semiconductor devices of the same type.
Inventors
- 👤 Takaji Takenaka
- 👤 Tositada Netsu
- 👤 Hidetaka Shigi
- 👤 Masakazu Yamamoto
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 19:13
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/611; H10W70/62; H10W70/63; H10W70/635; H10W70/67; H10W70/68; H10W70/685; H10W72/00; H10W72/01; H10W72/0198; H10W90/00; H10W90/701; H10W90/721; H10W90/724
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
199 words
A pin grid array type multi-chip module structure (10) comprising: a ceramic multi-layer wiring board (1) having opposing first and second surfaces; a plurality of connecting pads (6) arrayed on said first surface to mount a plurality of semiconductor devices (2 or 3) on said first surface; and a plurality of I/O pins (4) arrayed on said second surface and including a plurality of power supply I/O pins and a plurality of signal I/O pins, wherein said multi-layer wiring board is divided into area groups (A, B) having areas of different sizes, the area of individual groups being equal in accordance with the same type of semiconductor devices being supported on said board within said areas, and the arrayed arrangements of said connecting pads (6) and said I/O pins (4) are made identical for the individual areas of the same size and the positional relation between said identically arrayed connecting pads and the number of said identically arrayed I/O pins is made constant within the respective board areas of the same size, whereby metallized patterns inside said board which are to be connected to said power supply I/O pins are fixed for individual semiconductor devices of the same type.
Claim 2
Dependent Claim
199 words
A pin grid array type multi-chip module structure (10) comprising: a ceramic multi-layer wiring board (1) having opposing first and second surfaces; a plurality of connecting pads (6) arrayed on said first surface to mount a plurality of semiconductor devices (2 or 3) on said first surface; and a plurality of I/O pins (4) arrayed on said second surface and including a plurality of power supply I/O pins and a plurality of signal I/O pins, wherein said multi-layer wiring board is divided into area groups (A, B) having areas of different sizes, the area of individual groups being equal in accordance with the same type of semiconductor devices being supported on said board within said areas, and the arrayed arrangements of said connecting pads (6) and said I/O pins (4) are made identical for the individual areas of the same size and the positional relation between said identically arrayed connecting pads and the number of said identically arrayed I/O pins is made constant within the respective board areas of the same size, whereby metallized patterns inside said board which are to be connected to said power supply I/O pins are fixed for individual semiconductor devices of the same type.
Claim 3
Dependent Claim
25 words
A multi-chip module structure according to claim 1, wherein said power supply I/O pins (4) includes power voltage supply I/O pins and grounding I/O pins.
Claim 4
Dependent Claim
138 words
A multi-chip module structure according to Claim 1 wherein said board (1) includes: a top layer (5) having said connecting pads for mounting said semiconductor devices; an expansion layer (7) for transferring the grid pitch of said connecting pads to the grid pitch of through holes (20) inside said board; a plurality of signal wiring layers (8) for performing logical wiring between said semiconductor devices; a power supply layer (9) interposed between said signal wiring layers and having a metallized pattern adapted to supply power voltage and perform matching of characteristic impedances of signal conductors on said signal wiring layers; a conversion layer (11) for transferring the grid pitch of said through holes inside said board to the grid pitch of said I/O pins; and a bottom layer (12) having pads (13) for connection to said I/O pins.
References Cited (Backward Citations)
No citation records indexed.
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