EP0290672A1
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A semiconductor integrated circuit device
Assignee: Hitachi Ltd
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Filing: 1984-04-13
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Granted: —
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Expires: 2004-04-13
Abstract
Abstract A high speed and low power consumption semiconductor integrated circuit device has a plurality of basic cells (302) each being constructed by at least a plurality of bipolar transistors and a plurality of MOS transistors. One or more of said basic cells, adjacent to each other, are interconnected to form internal circuits such as a NAND gate or a flip-flop. A plurality of such internal circuits are connected in accordance with a logical diagram to form a single LSI.
Inventors
- 👤 Yoji Nishio
- 👤 Ikuro Masuda
- 👤 Kazuo Kato
- 👤 Shigeo Kuboki
- 👤 Masahiro Iwamura
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 15:48
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/996
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
101 words
A semiconductor integrated circuit device comprising: a semiconductor substrate (300) having a plurality of basic cell lines (303) arranged in parallel on one main plane thereof, said basic cell lines each including a plurality of basic cells (302) each including at least one transistor; a wiring pattern (304) disposed on said semiconductor substrate with an insulating layer being interleaved therebetween for making connections in each of said basic cells and among said basic cells, characterized in that each of said basic cells (302) is constructed by at least a plurality of bipolar transistors (20,21) and a plurality of MOS transistors (22,23;26,27).
Claim 2
Dependent Claim
101 words
A semiconductor integrated circuit device comprising: a semiconductor substrate (300) having a plurality of basic cell lines (303) arranged in parallel on one main plane thereof, said basic cell lines each including a plurality of basic cells (302) each including at least one transistor; a wiring pattern (304) disposed on said semiconductor substrate with an insulating layer being interleaved therebetween for making connections in each of said basic cells and among said basic cells, characterized in that each of said basic cells (302) is constructed by at least a plurality of bipolar transistors (20,21) and a plurality of MOS transistors (22,23;26,27).
Claim 3
Dependent Claim
104 words
. A semiconductor integrated circuit device according to Claim 1 wherein each of said basic cells (302) includes a bipolar transistor (20) having one main terminal thereof fixed to a highest potential (203) in the semiconductor substrate and a MOS transistor (22,23) in a common well formed in one main plane of the semiconductor substrate, a potential of said well being supplied from said one main terminal, a bipolar transistor (21) having one main terminal thereof connected to a potential (202) which varies during the operation, arranged in a different well (214) from said well, and a MOS transistor (26,27) arranged between said wells.
Claim 4
Dependent Claim
60 words
A semiconductor integrated circuit device according to Claim 2 wherein the other main terminal of said bipolar transistor having said one main terminal thereof fixed to the highest potential in the semiconductor substrate and said one main terminal of said bipolar transistor connected to the potential which varies during the circuit operation are interconnected by a metalized low resistance wiring.
Claim 5
Dependent Claim
33 words
A semiconductor integrated circuit device according to Claim 1 wherein a plurality of contacts are formed on a first insulation layer on a drain or a source of at least one MOS transistor.
Claim 6
Dependent Claim
36 words
A semiconductor integrated circuit device according to Claim 1 wherein a wiring connected to a control terminal of the bipolar transistor is narrower than a wiring connected to the other main terminal of the bipolar transistor.
Claim 7
Dependent Claim
43 words
A semiconductor integrated circuit device according to Claim 1 wherein at least one space for constructing a logic circuit is formed on each side of a highest potential power supply wiring and a lowest potential power supply wiring running above the MOS transistor.
Claim 8
Dependent Claim
38 words
A semiconductor integrated circuit device according to Claim 1 wherein at least one of said basic cells (302) includes a MOS basic cell (521) constructed by MOS transistors and a bipolar basic cell (522) constructed by bipolar transistors.
Claim 9
Dependent Claim
59 words
A semiconductor integrated circuit device according to Claim 7 wherein a plurality of said MOS basic cells (521) are arranged to form a MOS array (531,532;533,534) at least one said bipolar basic cell (522) is arranged to form a bipolar array, and at least one of said basic cell lines (511-517) includes said MOS array and said bipolar array.
Claim 10
Dependent Claim
27 words
A semiconductor integrated circuit device according to Claim 8 wherein the basic cells at opposite ends of the basic cell line are the bipolar basic cells (5231,523r).
Claim 11
Dependent Claim
36 words
A semiconductor integrated circuit device according to Claim 8 wherein each MOS array includes an even number of MOS basic (521) cells and each bipolar array (522) includes an even number of bipolar basic cells (645,646).
Claim 12
Dependent Claim
21 words
A semiconductor integrated circuit device according to Claim 8 wherein each MOS array (531,532;533,534) includes an even number of MOS transistors.
Claim 13
Dependent Claim
21 words
A semiconductor integrated circuit device according to Claim 8 wherein each bipolar array (522) includes an even number of bipolar transistors.
Claim 14
Dependent Claim
28 words
A semiconductor integrated circuit device according to claim 1, wherein one or more of said basic cells (302), adjacent to each other, are interconnected to form internal circuits.
Claim 15
Dependent Claim
65 words
A semiconductor integrated circuit device according to claim 13, wherein a plurality of input circuits (301) for receiving external input signals and supplying the received signals to said internal circuits and a plurality of output circuits (301) for receiving output signals from said internal circuits and externally supplying the output signals are being formed together with said internal circuits in a common semiconductor substrate (300).
References Cited (Backward Citations)
EP0110313A2
Cited
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