Fault-tolerant, error-correcting storage system and method for storing digital information in such a storage system

Claim 2

A storage device system for computers capable of dynamically and transparently reconstructing lost data characterized by: (a) A plurality of first individual storage devices (16) for storing digital information; (b) a second individual storage device (16′) for storing error/recovery code bits; (c) means for generating and storing error/recovery code bits in said second individual storage device (16′) according to a pre-defined error/recovery code checking algorithm for said digital information at corresponding respective bit positions across said plurality of first individual storage devices (16); and, (d) means for using said error/recovery code bits in combination with the contents of said corresponding respective bit positions across said plurality of first individual storage devices (16) to reconstruct a changed bit in error in said digital information according to said error/recovery code checking algorithm when one of said first and second individual storage devices (16, 16′) detects an error during the transfer of said digital information; and, if desired additionally comprising: (e) interface means (46, 56) disposed for receiving read and write requests from a user CPU (10); and, (f) a plurality of storage device controller means (601) connected between said interface means and respective ones of said plurality of storage device (16) for interfacing with said plurality of storage devices (16) and operating them concurrently.

Claim 3

A multiple storage device system for computers capable of concurrent operation from a single user device controller characterized by: (a) a plurality of first individual storage devices (16) for storing digital information; (b) interface means (46, 56) disposed for receiving read and write requests from a user CPU (10, 54) via the single user device controller (14, 60); and, (c) a plurality of storage device controller means (601) connected between said interface (46, 56) and respective ones of said plurality of storage devices (16) for interfacing with said plurality of storage devices (16) and operating them concurrently; and, if desired additionally comprising: (d) a second individual storage device (16′) for storing error/recovery code bits; (e) means for generating and storing error/recovery code bits in said second individual storage device (16′) according to a pre-defined error/recovery code checking algorithm for said digital information at corresponding respective bit positions across said plurality of first individual storage devices (16); and, (f) means for using said error/recovery code bits in combination with the contents of said corresponding respective bit positions across said plurality of first individual storage devices (16) to reconstruct a changed bit in error in said digital information according to said error/recovery code checking algorithm when one of said first and second individual storage devices (16, 16′) detects an error during the transfer of said digital information.

Claim 4

A multiple storage device system for computers capable of concurrent operation from a single user device controller characterized by: (a) a plurality of first individual storage devices (16) for storing digital information; (b) interface means (46, 56) disposed for receiving read and write requests from a user CPU (10, 54) via the single user device controller (14, 60); and, (c) a plurality of storage device controller means (601) connected between said interface (46, 56) and respective ones of said plurality of storage devices (16) for interfacing with said plurality of storage devices (16) and operating them concurrently; and, if desired additionally comprising: (d) a second individual storage device (16′) for storing error/recovery code bits; (e) means for generating and storing error/recovery code bits in said second individual storage device (16′) according to a pre-defined error/recovery code checking algorithm for said digital information at corresponding respective bit positions across said plurality of first individual storage devices (16); and, (f) means for using said error/recovery code bits in combination with the contents of said corresponding respective bit positions across said plurality of first individual storage devices (16) to reconstruct a changed bit in error in said digital information according to said error/recovery code checking algorithm when one of said first and second individual storage devices (16, 16′) detects an error during the transfer of said digital information.

Claim 9

An intelligent virtual mass storage device for a computer capable of reconstructing lost data and characterized by: (a) a single interface logic portion for interfacing with a user CPU (10, 54), said interfacing logic portion including system device controller interface means (43, 62) for interfacing with a device controller (14, 60) through which the user CPU (10, 54) is connected to the mass storage device (40); (b) a plurality of individually, asynchronously operable mass storage devices (16) adapted to interface with a said device controller (60′) at an input interface thereof; (c) device controller means (60′) for connecting between said interfacing logic portion and said plurality of mass storage devices (16), said device controller means (60′) including controller interface means for presenting a system device controller interface to said input interface of said mass storage device (16); (d) data buffer means (68) for transferring data to and from said mass storage device (16); (e) error/recovery generator bit means for generating and storing error/recovery code bits in a dedicated one of said mass storage devices according to a pre-defined error/recovery code checking algorithm for digital information at corresponding respective bit positions across said plurality of mass storage devices (16); and, (f) reconstruct logic means (76) for using said error/recovery code bits in combination with the contents of said corresponding respective bit positions across said plurality of mass storage devices (16) to reconstruct a changed bit in error in said digital information according to said error/recovery code checking algorithm when one of said mass storage devices (16, 16′) detects an error during the transfer of said digital information; and, characterized in that (g) said device controller means (60′) preferably comprises a plurality of storage device controllers (60′) connected to respective ones of said plurality of mass storage devices (16) whereby said mass storage devices (16) are operable concurrently.

Claim 10

An intelligent virtual mass storage device for a computer capable of reconstructing lost data and characterized by: (a) a single interface logic portion for interfacing with a user CPU (10, 54), said interfacing logic portion including system device controller interface means (43, 62) for interfacing with a device controller (14, 60) through which the user CPU (10, 54) is connected to the mass storage device (40); (b) a plurality of individually, asynchronously operable mass storage devices (16) adapted to interface with a said device controller (60′) at an input interface thereof; (c) device controller means (60′) for connecting between said interfacing logic portion and said plurality of mass storage devices (16), said device controller means (60′) including controller interface means for presenting a system device controller interface to said input interface of said mass storage device (16); (d) data buffer means (68) for transferring data to and from said mass storage device (16); (e) error/recovery generator bit means for generating and storing error/recovery code bits in a dedicated one of said mass storage devices according to a pre-defined error/recovery code checking algorithm for digital information at corresponding respective bit positions across said plurality of mass storage devices (16); and, (f) reconstruct logic means (76) for using said error/recovery code bits in combination with the contents of said corresponding respective bit positions across said plurality of mass storage devices (16) to reconstruct a changed bit in error in said digital information according to said error/recovery code checking algorithm when one of said mass storage devices (16, 16′) detects an error during the transfer of said digital information; and, characterized in that (g) said device controller means (60′) preferably comprises a plurality of storage device controllers (60′) connected to respective ones of said plurality of mass storage devices (16) whereby said mass storage devices (16) are operable concurrently.

Claim 11

A virtual mass storage device for a computer characterized by: (a) a single interfacing logic portion for interfacing with a user CPU (10, 54), said interfacing logic portion including system device controller interface means (43, 62) for interfacing with a standard system device controller (14, 60) through which the user CPU (10, 54) is connected to the virtual mass storage device (40); (b) a plurality of standard mass storage devices (16) adapted to interface with a standard system device controller (14, 60) at an input interface thereof; (c) a plurality of device controllers (60′) connected between said interfacing logic portion and respective ones of said plurality of mass storage devices (16), each of said device controllers (60′) including controller interface means for presenting a standard system device controller interface to said input interface of its respective mass storage device (16), and a data buffer (68) for transferring data to and from its respective mass storage device (16); and, (d) said interfacing logic portion including a control portion having CPU means (44) operably connected to said plurality of device controllers (60′) for controlling a concurrent sequence of operation of said device controllers (60′) in writing data to and reading data from said mass storage devices (16); and wherein said mass storage device preferably additionally comprises: (e) error/recovery generator bit means for generating and storing error/recovery code bits in a dedicated one of said mass storage devices (16) according to a pre-defined error/recovery code checking algorithm for digital information at corresponding respective bit positions across said plurality of mass storage devices (16); and (f) reconstruct logic means (76) for using said error/recovery code bits in combination with the contents of said corresponding respective bit positions across said plurality of mass storage devices (16) to reconstruct a changed bit in error in said digital information according to said error/recovery code checking algorithm when one of said mass storage devices (16, 16′) detects an error during the transfer of said digital information, and wherein said reconstruct logic means (76) preferably includes means for sensing an error condition from one of said mass storage devices (16, 16′) in the transfer of data and for using the knowledge of which of said mass storage devices' data is in error as an indication of which bit position is in error in combination with the said error/recovery bit associated with the data in error containing the erroneous bit to logically reconstruct said erroneous bit.

Claim 12

A virtual mass storage device for a computer characterized by: (a) a single interfacing logic portion for interfacing with a user CPU (10, 54), said interfacing logic portion including system device controller interface means (43, 62) for interfacing with a standard system device controller (14, 60) through which the user CPU (10, 54) is connected to the virtual mass storage device (40); (b) a plurality of standard mass storage devices (16) adapted to interface with a standard system device controller (14, 60) at an input interface thereof; (c) a plurality of device controllers (60′) connected between said interfacing logic portion and respective ones of said plurality of mass storage devices (16), each of said device controllers (60′) including controller interface means for presenting a standard system device controller interface to said input interface of its respective mass storage device (16), and a data buffer (68) for transferring data to and from its respective mass storage device (16); and, (d) said interfacing logic portion including a control portion having CPU means (44) operably connected to said plurality of device controllers (60′) for controlling a concurrent sequence of operation of said device controllers (60′) in writing data to and reading data from said mass storage devices (16); and wherein said mass storage device preferably additionally comprises: (e) error/recovery generator bit means for generating and storing error/recovery code bits in a dedicated one of said mass storage devices (16) according to a pre-defined error/recovery code checking algorithm for digital information at corresponding respective bit positions across said plurality of mass storage devices (16); and (f) reconstruct logic means (76) for using said error/recovery code bits in combination with the contents of said corresponding respective bit positions across said plurality of mass storage devices (16) to reconstruct a changed bit in error in said digital information according to said error/recovery code checking algorithm when one of said mass storage devices (16, 16′) detects an error during the transfer of said digital information, and wherein said reconstruct logic means (76) preferably includes means for sensing an error condition from one of said mass storage devices (16, 16′) in the transfer of data and for using the knowledge of which of said mass storage devices' data is in error as an indication of which bit position is in error in combination with the said error/recovery bit associated with the data in error containing the erroneous bit to logically reconstruct said erroneous bit.

Claim 13

A storage device system (40) for computers capable of dynamically and transparently reconstructing lost data characterized by: (a) a plurality of first individual storage devices (16) for storing digital information; (b) a second individual storage device (16′) for storing error/recovery code bits; (c) means for generating and storing error/recovery code bits in said second individual storage device (16′) according to a pre-defined parity checking algorithm for said digital information at corresponding respective bit positions across said plurality of first individual storage devices (16); (d) means for using said error/recovery code bits in combination with the contents of said corresponding respective bit positions across said plurality of first individual storage devices (16) to reconstruct a changed bit in error in said digital information according to said parity checking algorithm when one of said first and second individual storage devices (16, 16′) detects an error during the transfer of said digital information; (e) interface means (14, 18, 46, 56, 62) disposed for receiving read and write requests from a user CPU (10, 54); and, (f) a plurality of storage device controller means (60′) connected between said interface means (14, 18, 46, 56, 62) and respective ones of said plurality of storage devices (16) for interfacing with said plurality of storage devices (16) and operating them concurrently, characterized in that, (g) said interface means (14, 18, 46, 56, 62) includes interface definition means for accepting requests from a user CPU (10, 54) according to a first interface convention and for translating said requests into a second interface convention used by said storage device controller means (60′) for interfacing with said plurality of storage devices (16).

Claim 14

A storage device system (40) for computers capable of dynamically and transparently reconstructing lost data characterized by: (a) a plurality of first individual storage devices (16) for storing digital information; (b) a second individual storage device (16′) for storing error/recovery code bits; (c) means for generating and storing error/recovery code bits in said second individual storage device (16′) according to a pre-defined parity checking algorithm for said digital information at corresponding respective bit positions across said plurality of first individual storage devices (16); (d) means for using said error/recovery code bits in combination with the contents of said corresponding respective bit positions across said plurality of first individual storage devices (16) to reconstruct a changed bit in error in said digital information according to said parity checking algorithm when one of said first and second individual storage devices (16, 16′) detects an error during the transfer of said digital information; (e) interface means (14, 18, 46, 56, 62) disposed for receiving read and write requests from a user CPU (10, 54); and, (f) a plurality of storage device controller means (60′) connected between said interface means (14, 18, 46, 56, 62) and respective ones of said plurality of storage devices (16) for interfacing with said plurality of storage devices (16) and operating them concurrently, characterized in that, (g) said interface means (14, 18, 46, 56, 62) includes interface definition means for accepting requests from a user CPU (10, 54) according to a first interface convention and for translating said requests into a second interface convention used by said storage device controller means (60′) for interfacing with said plurality of storage devices (16).

Claim 15

The storage device system of claim 7 and characterized by one or more of the following features: (a) said interface means (14, 18, 46, 56, 62) including a control portion (43) having CPU means (44) operably connected to said plurality of storage device controller means (60′) for controlling the sequence of operation of said storage device controller means (60′) in writing data to and reading data from said storage devices (16). (b) a plurality of data buffers (68) connected to respective ones of said plurality of storage devices (16) from which data is written and into which data is read with respect to the associated said storage device. (c) a buffer memory (64) into which data to be written to all said storage devices (16) is placed prior to being transferred to a said data buffer (68) for transferring said data to a said associated storage device (16); and wherein, said CPU means (44) includes logic (48) for immediately acknowledging a write to said associated storage device upon said data being placed in said buffer memory (64), and wherein said CPU means (44) preferably includes logic (48) for checking data in said buffer memory (64) and indicating it as having been read from an associated storage device (16) without an actual read thereof when a read request therefor is received from a user CPU whereby said buffer memory (64) acts as a cache memory in such cases, and if desired, battery backup power supply means (78) operably connected to said buffer memory (64) for maintaining the data therein in the event of a power failure to the storage device system.

Claim 22

The method of claim 11 characterized by concurrently operating multiple storage devices and reconstruction of lost data by additionally comprising the steps of: (a) providing a plurality of the storage devices (16) for storing digital information; (b) providing an extra storage device (16′) for storing error/recovery code bits; (c) operably connecting a plurality of the storage device controller means (60′) between the interface means and respective ones of the plurality of storage devices (16) and the extra storage device (16′); (d) generating and storing error/recovery code bits in the extra storage device (16′) according to a pre-defined error/recovery code checking algorithm for the digital information at corresponding respective bit positions across the plurality of the storage devices; and, (e) using the error/recovery code bits in combination with the contents of the corresponding respective bit positions across the plurality of the storage devices (16) to reconstruct a changed bit in error in the digital information according to the error/recovery code checking algorithm when one of the storage devices (16) detects an error during the transfer of the digital information; and, if desired (f) including a control portion within the interface means having a CPU (44) operably connected to the plurality of storage device controllers (60′) to control the sequence of operation of the storage device controllers (60′) in writing data to and reading data from the storage devices (16); and if further desired, (g) connecting a plurality of data buffers (68) to respective ones of the plurality of storage devices (16) from which data is written and into which data is read with respect to the associated storage device (16); and, if still further desired (h) providing a buffer memory (64) into which data to be written to all the storage devices (16) is placed prior to being transferred to a data buffer (68) for transferring the data to an associated storage device (16); and, immediately acknowledging a write to the associated storage device upon the data being placed in the buffer memory (64); and, if yet still further 80 desired, (i) checking data in the buffer memory (64) and indicating it as having been read from an associated storage device (16) without an actual read thereof when a read request therefor is received from a user whereby the buffer memory (64) acts as a cache memory in such cases.

Claim 23

An intelligent virtual mass storage device for a computer capable of reconstructing lost data and characterized by: (a) a single interfacing logic portion for interfacing with a user CPU (10, 54), said interfacing logic portion including system device controller interface means for interfacing with a device controller (60′) through which the user CPU (10, 54) is connected to the mass storage device (40); (b) a plurality of individually, asynchronously operable mass storage devices (16) adapted to interface with a said device controller (60′) at an input interface thereof; (c) device controller means (60′) for connecting between said interfacing logic portion and said plurality of mass storage devices (16), said device controller means (60′) including controller interface means (62) for presenting a system device controller interface to said input interface of said mass storage devices (16); (d) data buffer means (68) for transferring data to and from said mass storage devices; (e) error/recovery generator bit means for generating and storing error/recovery code bits in a dedicated one of said mass storage devices (16′) according to a pre-defined error/recovery code checking algorithm for digital information at corresponding respective bit positions across said plurality of mass storage devices; (f) reconstruct logic means (76) for using said error/recovery code bits in combination with the contents of said corresponding respective bit positions across said plurality of mass storage devices to reconstruct a changed bit in error in said digital information according to said error/recovery code checking algorithm when one of said mass storage devices (16, 16′) detects an error during the transfer of said digital information; wherein, (g) said device controller means (60′) comprises a plurality of storage device controllers (60′) connected to respective ones of said plurality of mass storage devices (16) whereby said mass storage devices (16) are operable concurrently; and, (h) said interfacing logic portion includes a control portion having CPU means (44) operably connected to said plurality of device controllers (60′) for controlling the sequence of operation of said device controllers (60′) in writing data to and reading data from said mass storage devices (16).

Claim 24

An intelligent virtual mass storage device for a computer capable of reconstructing lost data and characterized by: (a) a single interfacing logic portion for interfacing with a user CPU (10, 54), said interfacing logic portion including system device controller interface means for interfacing with a device controller (60′) through which the user CPU (10, 54) is connected to the mass storage device (40); (b) a plurality of individually, asynchronously operable mass storage devices (16) adapted to interface with a said device controller (60′) at an input interface thereof; (c) device controller means (60′) for connecting between said interfacing logic portion and said plurality of mass storage devices (16), said device controller means (60′) including controller interface means (62) for presenting a system device controller interface to said input interface of said mass storage devices (16); (d) data buffer means (68) for transferring data to and from said mass storage devices; (e) error/recovery generator bit means for generating and storing error/recovery code bits in a dedicated one of said mass storage devices (16′) according to a pre-defined error/recovery code checking algorithm for digital information at corresponding respective bit positions across said plurality of mass storage devices; (f) reconstruct logic means (76) for using said error/recovery code bits in combination with the contents of said corresponding respective bit positions across said plurality of mass storage devices to reconstruct a changed bit in error in said digital information according to said error/recovery code checking algorithm when one of said mass storage devices (16, 16′) detects an error during the transfer of said digital information; wherein, (g) said device controller means (60′) comprises a plurality of storage device controllers (60′) connected to respective ones of said plurality of mass storage devices (16) whereby said mass storage devices (16) are operable concurrently; and, (h) said interfacing logic portion includes a control portion having CPU means (44) operably connected to said plurality of device controllers (60′) for controlling the sequence of operation of said device controllers (60′) in writing data to and reading data from said mass storage devices (16).

Claim 25

The virtual mass storage device for a computer of claim 13 characterized by one or more of the following features: (a) said data buffer means (68) comprises a plurality of data buffers (68) connected to respective ones of said plurality of storage devices (16) from which data is written and into which data is read with respect to the associated said storage device (16); (b) said interface means includes interface definition means for accepting requests from a user CPU (10, 54) according to a first interface convention and for translating said requests into a second interface convention used by said storage device controller means (60′) for interfacing with said plurality of storage devices (16); (c) a buffer memory (64) into which data to be written to all said mass storage devices (16) is placed prior to being transferred to a said data buffer (68) for transferring said data to a said associated mass storage device (16); and wherein said CPU means (44) includes logic for immediately acknowledging a write to said associated mass storage device (16) upon said data being placed in said buffer memory (64) and, if desired said CPU means (44) also includes logic for checking data in said buffer memory (64) and indicating it as having been read from an associated mass storage device (16) without an actual read thereof when a read request therefor is received from a user whereby said buffer memory (64) acts as a cache memory in such cases; and (d) said plurality of device controllers (60′), said controller interface means (62), said data buffers (68), and said interfacing logic portion are interconnected to communicate with one another over a first computer BUS (46); and, said error/recovery generator bit means (72, 74) and said reconstruct logic means (76) are interconnected to communicate with one another over a second computer BUS (50).

Claim 26

A virtual mass storage device (40) for a computer characterized by: (a) a single interfacing logic portion for interfacing with a user CPU (10, 54), said interfacing logic portion including system device controller interface means (62) for interfacing with a standard system device controller (60) through which the user CPU (10, 54) is connected to the virtual mass storage device (40); (b) a plurality of standard mass storage devices (16) adapted to interface with a standard system device controller (60) at an input interface thereof; (c) a plurality of device controllers (60′) connected between said interfacing logic portion (56) and respective ones of said plurality of mass storage devices (16), each of said device controllers (60′) including controller interface means for presenting a standard system device controller interface to said input interface of its respective mass storage device (16), and a data buffer (68) for transferring data to and from its respective mass storage device (16); (d) said interfacing logic portion including a control portion having CPU means (44) operably connected to said plurality of device controllers (60′) for controlling a concurrent sequence of operation of said device controllers (60′) in writing data to and reading data from said mass storage devices (16); (e) error/recovery generator bit means for generating and storing error/recovery code bits in a dedicated one of said mass storage devices (16) according to a pre-defined error/recovery code checking algorithm for digital information at corresponding respective bit positions across said plurality of mass storage devices (16); (f) reconstruct logic means (76) for using said error/recovery code bits in combination with the contents of said corresponding respective bit positions across said plurality of mass storage devices (16) to reconstruct a changed bit in error in said digital information according to said error/recovery code checking algorithm when one of said mass storage devices (16) detects an error during the transfer of said digital information; characterized in that (g) said reconstruct logic means (76) includes means for sensing an error condition from one of said mass storage devices (16) in the transfer of data and for using the knowledge of which of said mass storage devices′ data is in error as an indication of which bit position is in error in combination with the said error/recovery bit associated with the data in error containing the erroneous bit to logically reconstruct said erroneous bit; and additionally comprising, (h) a buffer memory (64) into which data to be written to all said mass storage devices (16) is placed prior to being transferred to a said data buffer (68) for transferring said data to a said associated mass storage device (16); and characterized in that (i) said CPU means (44) includes logic for immediately acknowledging a write to said associated mass storage device (16) upon said data being placed in said buffer (64); and, if desired said CPU means (44) also includes logic for checking data in said buffer memory (64) and indicating it as having been read from an associated mass storage device (16) without an actual read thereof when a read request therefor is received from a user (54) whereby said buffer memory (64) acts as a cache memory in such cases.

Claim 27

A virtual mass storage device (40) for a computer characterized by: (a) a single interfacing logic portion for interfacing with a user CPU (10, 54), said interfacing logic portion including system device controller interface means (62) for interfacing with a standard system device controller (60) through which the user CPU (10, 54) is connected to the virtual mass storage device (40); (b) a plurality of standard mass storage devices (16) adapted to interface with a standard system device controller (60) at an input interface thereof; (c) a plurality of device controllers (60′) connected between said interfacing logic portion (56) and respective ones of said plurality of mass storage devices (16), each of said device controllers (60′) including controller interface means for presenting a standard system device controller interface to said input interface of its respective mass storage device (16), and a data buffer (68) for transferring data to and from its respective mass storage device (16); (d) said interfacing logic portion including a control portion having CPU means (44) operably connected to said plurality of device controllers (60′) for controlling a concurrent sequence of operation of said device controllers (60′) in writing data to and reading data from said mass storage devices (16); (e) error/recovery generator bit means for generating and storing error/recovery code bits in a dedicated one of said mass storage devices (16) according to a pre-defined error/recovery code checking algorithm for digital information at corresponding respective bit positions across said plurality of mass storage devices (16); (f) reconstruct logic means (76) for using said error/recovery code bits in combination with the contents of said corresponding respective bit positions across said plurality of mass storage devices (16) to reconstruct a changed bit in error in said digital information according to said error/recovery code checking algorithm when one of said mass storage devices (16) detects an error during the transfer of said digital information; characterized in that (g) said reconstruct logic means (76) includes means for sensing an error condition from one of said mass storage devices (16) in the transfer of data and for using the knowledge of which of said mass storage devices′ data is in error as an indication of which bit position is in error in combination with the said error/recovery bit associated with the data in error containing the erroneous bit to logically reconstruct said erroneous bit; and additionally comprising, (h) a buffer memory (64) into which data to be written to all said mass storage devices (16) is placed prior to being transferred to a said data buffer (68) for transferring said data to a said associated mass storage device (16); and characterized in that (i) said CPU means (44) includes logic for immediately acknowledging a write to said associated mass storage device (16) upon said data being placed in said buffer (64); and, if desired said CPU means (44) also includes logic for checking data in said buffer memory (64) and indicating it as having been read from an associated mass storage device (16) without an actual read thereof when a read request therefor is received from a user (54) whereby said buffer memory (64) acts as a cache memory in such cases.