← Back to Patent Explorer
EP0315209A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Microcomputer incorporating memory

Assignee: Toshiba Corp
•
Filing: 1988-11-04
•
Granted: —
•
Expires: 2008-11-04
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A microcomputer (18) of this invention includes an internal memory (3, 4). These memories are connected to internal buses (21, 22, 23, 41, 43, 45) and external buses (31, 32, 33, 34) through bi-directional buffers (7, 8, 9). This microcomputer also includes a buffer controller (10) for determining whether an access by a control section (2) is made to the internal memory (3, 4) or the access is made to an external memory (40). When the control section (2) accesses the internal memories (3, 4), the buffer controller (10) controls the directions of the bi-directional buffers (7, 8, 9) to enable data transfer from the external to the internal bus side. When the controller accesses the external memory, bi-directional buffers (7, 8, 9) are controlled to enable data transfer from the internal to the exter­nal bus side.

Inventors

  • 👤 Yasuo C/O Patent Division Iijima

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-01 15:08
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F11/00; G06F11/07; G06F11/0703; G06F11/0751; G06F11/0754; G06F11/076; G06F12/00; G06F12/14; G06F12/1416; G06F12/1425; G06F12/1433; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/46

Claims Analysis

Total Claims: 14
Claim 1
Independent Claim 57 words
A microcomputer comprising memory means (3, 4) for storing data; memory access means (2, 11) for accessing said memory means; and input/output means for externally inputting/outputting data, characterized in that there is provided: output inhibiting means (7, 8, 9) for inhibiting external output through input/output means of data derived from an access operation to said memory means.
Claim 2
Dependent Claim 57 words
A microcomputer comprising memory means (3, 4) for storing data; memory access means (2, 11) for accessing said memory means; and input/output means for externally inputting/outputting data, characterized in that there is provided: output inhibiting means (7, 8, 9) for inhibiting external output through input/output means of data derived from an access operation to said memory means.
Claim 3
Dependent Claim 20 words
A microcomputer according to claim 1, charac­terized in that the access is performed from said memory access means (2, 11).
Claim 4
Dependent Claim 108 words
A microcomputer according to claim 1, charac­terized by further comprising: access source determining means (2, 11) for deter­mining that the access is performed from said memory access means or is externally performed through said input/output means; and control means (10) for controlling said output inhibiting means (7, 8, 9) to inhibit external output through said input/output means of data derived from the access to said output inhibiting means when the access is performed from said memory access means, and for controlling said output inhibiting means to allow exter­nal output through said input/output means of data derived from the access when the access is performed from outside said microcomputer.
Claim 5
Dependent Claim 95 words
A microcomputer according to claim 1, charac­terized by further comprising access source determining means (2, 11) for determining that the access is per­formed from said memory access means or is externally performed through said input/output means, wherein said memory means (3, 4) comprises a program memory (3) for storing programs, and a data memory (4) for storing data, and said output inhibiting means is controlled so that the read data may not be externally output through said input/output means when the contents of said program or data memory are read by said memory access means.
Claim 6
Dependent Claim 105 words
A microcomputer according to claim 1, charac­terized by further comprising access source determining means for determining that the access is performed from said memory access means or is externally performed through said input/output means to control said output inhibiting means so as to block external output through said input/output means of data read out from said program memory when the access is externally performed to said program memory in a read mode, and so as to allow external output of the data read out from said data memory through said input/output means when the access is performed to said data memory in a read mode.
Claim 7
Dependent Claim 50 words
A microcomputer according to claim 1, charac­terized in that said output inhibiting means comprises a bi-directional buffer, and said input/output means comprises internal bus means for connecting said memory means to said bi-directional buffer; and external bus means for connecting said bi-­directional buffer to an external portion of said microcomputer.
Claim 8
Dependent Claim 20 words
A microcomputer according to claim 6, charac­terized by further comprising control means for controlling transfer directions of said bi-directional buffers.
Claim 9
Dependent Claim 41 words
A microcomputer according to claim 7, charac­terized in that each of said internal and external bus means comprises an access data bus, an address bus, and a data bus, respectively, and said bi-directional buffer is arranged for each of said buses.
Claim 10
Dependent Claim 25 words
A microcomputer according to claim 3, charac­terized in that a test unit is further provided being connected to said microcomputer to access said memory means.
Claim 11
Dependent Claim 32 words
A microcomputer according to claim 3, characterized in that external memory is further pro­vided being externally connected to said microcomputer, and said memory access means accesses said memory and external memory means.
Claim 12
Dependent Claim 109 words
A microcomputer according to claim 8, charac­terized in that an external memory is further provided being connected to said microcomputer, said control means controls said bi-directional buffers of said data buses to disable data transfer when said memory access means accesses said memory means, and said control means controls the directions of said bi-directional buffers of said access data and address buses to enable data transfer from said internal bus means to said external bus means and controls said bi-directional buffer of said input/output data bus to enable data transfer from said external bus means to said internal bus means when said memory access means read-accesses said external memory.
Claim 13
Dependent Claim 80 words
A microcomputer according to claim 8, charac­terized in that a test unit is selectively connected to said microcomputer, said control means controls said bi-­directional buffers of said access and address buses to enable data transfer from said external bus means to said internal bus means, and controls the direction of said bi-directional buffer of said input/output data bus to enable data transfer from said internal bus means to said external bus means, when said test unit read-­accesses said memory means.
Claim 14
Dependent Claim 10 words
An IC card incorporating a microcomputer according to claim 1.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag