EP0318930A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Voltage controlled oscillator
Assignee: Toshiba Corp
•
Filing: 1988-11-29
•
Granted: —
•
Expires: 2008-11-29
Abstract
Abstract A voltage controlled oscillator comprises a phase locked loop section (1) and a voltage controlled oscillator section (2). The phase locked loop section (1) is coupled with an input signal (Fref) at a reference frequency and a reference potential (Vref), and performs a signal feedback control so as to obtain a constant delay time of a first variable delay circuit (3) contained in the phase locked loop section. The voltage controlled oscillator section (2) controls a delay time of a second variable delay circuit (10) in a ring oscillator by a control input voltage (Vcont) and an output voltage (Voff) of a low-pass filter (7) contained in the phase locked loop section, and produces a signal oscillating at a frequency as determined by the delay time. In the voltage controlled oscillator thus arranged, the output frequency is determined by controlling a delay time of the second variable delay circuit in the voltage controlled oscillator section. Since the delay time is accurately controlled by the phase locked loop section, the obtained output frequency is stable against the variance of the process parameters. Since the delay time is varied by the reference frequency of the input signal, the output frequency may be set at a desired frequency, and hence a frequency band of the oscillation frequencies may also be set appropriately.
Inventors
- 👤 Kenji C/O Patent Division Matsuo
- 👤 Ikuo Tsuchiya
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 09:33
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/085; H03L7/089; H03L7/0891
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
118 words
A voltage controlled oscillator comprising: a phase locked loop section (1) coupled with an input signal (Fref) at a reference frequency and a reference potential (Vref), said phase locked loop section performing a signal feedback control so as to obtain a constant delay time of a first variable delay circuit (3) contained in said phase locked loop section; and a voltage controlled oscillator section (2) for controlling a delay time of a second variable delay circuit (10) in a ring oscillator by a control input voltage (Vcont) and an output voltage (Voff) of a low-pass filter (7) contained in said phase locked loop section, and producing a signal oscillating at a frequency as determined by the delay time.
Claim 2
Dependent Claim
118 words
A voltage controlled oscillator comprising: a phase locked loop section (1) coupled with an input signal (Fref) at a reference frequency and a reference potential (Vref), said phase locked loop section performing a signal feedback control so as to obtain a constant delay time of a first variable delay circuit (3) contained in said phase locked loop section; and a voltage controlled oscillator section (2) for controlling a delay time of a second variable delay circuit (10) in a ring oscillator by a control input voltage (Vcont) and an output voltage (Voff) of a low-pass filter (7) contained in said phase locked loop section, and producing a signal oscillating at a frequency as determined by the delay time.
Claim 3
Dependent Claim
32 words
A voltage controlled oscillator according to claim 1, characterized in that said first and second variable delay circuits (3, 10) are constructed with a plurality of basic delay circuits containing equal constants.
Claim 4
Dependent Claim
42 words
A voltage controlled oscillator according to claim 1, characterized in that a delay time of said second variable delay circuit (10) is controlled by a signal resulting from the level conversion of said control voltage input (Vcont) and said output voltage (Voff).
Claim 5
Dependent Claim
32 words
A voltage controlled oscillator according to claim 3, characterized in that said first and second variable delay circuits (3, 10) are constructed with a plurality of basic delay circuits containing equal constants.
Claim 6
Dependent Claim
170 words
A voltage controlled oscillator comprising: a phase locked loop including a first variable delay circuit (3) coupled for reception with an input signal (Fref) at a reference frequency, a phase comparing means (4, 6, 7) for comparing the output signal (NDO) of said first variable delay circuit (3) and said input signal (Fref), and outputting an output voltage (Voff) according to the comparison result, and a feedback circuit (PV, NV) for applying said output voltage (Voff) and said reference potential (Vref) to said first variable delay circuit (3), thereby to control a delay of said first variable delay circuit (3); a voltage controlled oscillator section including a ring oscillator for producing a frequency output (FVCO), said ring oscillator containing a second variable delay circuit (10), and a feedback loop (PV, NV) for applying the output voltage (Voff) of said phase comparing means (4, 6, 7) and the control voltage (Vcont) to said second variable delay circuit (10), thereby to control a delay time of said second variable delay circuit (10).
Claim 7
Dependent Claim
170 words
A voltage controlled oscillator comprising: a phase locked loop including a first variable delay circuit (3) coupled for reception with an input signal (Fref) at a reference frequency, a phase comparing means (4, 6, 7) for comparing the output signal (NDO) of said first variable delay circuit (3) and said input signal (Fref), and outputting an output voltage (Voff) according to the comparison result, and a feedback circuit (PV, NV) for applying said output voltage (Voff) and said reference potential (Vref) to said first variable delay circuit (3), thereby to control a delay of said first variable delay circuit (3); a voltage controlled oscillator section including a ring oscillator for producing a frequency output (FVCO), said ring oscillator containing a second variable delay circuit (10), and a feedback loop (PV, NV) for applying the output voltage (Voff) of said phase comparing means (4, 6, 7) and the control voltage (Vcont) to said second variable delay circuit (10), thereby to control a delay time of said second variable delay circuit (10).
Claim 8
Dependent Claim
32 words
A voltage controlled oscillator according to claim 5, characterized in that said first and second variable delay circuits (3, 10) are constructed with a plurality of basic delay circuits containing equal constants.
Claim 9
Dependent Claim
45 words
A voltage controlled oscillator according to claim 5, characterized in that said ring oscillator includes a looped circuit made up of said second variable delay circuit (10) and an inverter (11) for inverting a phase of the output signal of said second variable delay circuit.
Claim 10
Dependent Claim
178 words
A voltage controlled oscillator comprising: a phase locked loop including a first variable delay circuit (3) coupled for reception with an input signal (Fref) at a reference frequency, a phase comparing means (4, 6, 7) for comparing the output signal (NDO) of said first variable delay circuit (3) and said input signal (Fref), and outputting an output voltage (Voff) according to the comparison result, and a feedback loop for level converting said output voltage (Voff) and said reference potential (Vref) and applying the level converted output signals (PV, NV) to said first variable delay circuit (3), thereby to control a delay time of said first variable delay circuit (3); a voltage controlled oscillator section including a ring oscillator for producing a frequency output (FVCO), said ring oscillator containing a second variable delay circuit (10), and a feedback loop for level converting said output voltage (Voff) and a control voltage (Vcont) and applying the level converted output signals (PV, NV) to said second variable delay circuit (10), thereby to control a delay of said second variable delay circuit (10).
Claim 11
Dependent Claim
178 words
A voltage controlled oscillator comprising: a phase locked loop including a first variable delay circuit (3) coupled for reception with an input signal (Fref) at a reference frequency, a phase comparing means (4, 6, 7) for comparing the output signal (NDO) of said first variable delay circuit (3) and said input signal (Fref), and outputting an output voltage (Voff) according to the comparison result, and a feedback loop for level converting said output voltage (Voff) and said reference potential (Vref) and applying the level converted output signals (PV, NV) to said first variable delay circuit (3), thereby to control a delay time of said first variable delay circuit (3); a voltage controlled oscillator section including a ring oscillator for producing a frequency output (FVCO), said ring oscillator containing a second variable delay circuit (10), and a feedback loop for level converting said output voltage (Voff) and a control voltage (Vcont) and applying the level converted output signals (PV, NV) to said second variable delay circuit (10), thereby to control a delay of said second variable delay circuit (10).
Claim 12
Dependent Claim
32 words
A voltage controlled oscillator according to claim 8, characterized in that said first and second variable delay circuits (3, 10) are constructed with a plurality of basic delay circuits containing equal constants.
Claim 13
Dependent Claim
45 words
A voltage controlled oscillator according to claim 8, characterized in that said ring oscillator includes a looped circuit made up of said second variable delay circuit (10) and an inverter (11) for inverting a phase of the output signal of said second variable delay circuit.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.