Bias and precharging circuit for a bit line of EPROM memory cells in CMOS technology

Abstract

Abstract The bias and precharging circuit comprises a bias part (5) and a precharging part (6) of the bit line (1) together with a sensing amplifier (7) operating by comparison of the voltage of the bit line (1) and a dummy bit line (2). The precharging part (6) comprises means (21) for turning off the bias and precharging parts (5, 6) as soon as the sensing amplifier (7) has read the cell subjected to precharging. The bias part (5) comprises means (16) for amplifying the voltage unbalance produced by bias between the bit line (1) and the dummy bit line (2). It provides current-mirror means (13, 14, 15) to cause said voltage unbalance independently of the precharging part (6).

Inventors

• 👤 Maurizio Secol
• 👤 Maurizio Gaibotti

Bibliographic Details