Time division switching for multi-channel calls using two time switch memories acting as a frame aligner

Claim 2

A time division switching system for multi-channel calls, comprising: an incoming highway for supporting an incoming frame having time slots in which signals of said multi-channel calls are carried; an outgoing highway for supporting an outgoing frame having time slots in which corresponding signals of said multi-channel calls are carried; first and second time switch memories each having memory locations corresponding to the time slots of each of said incoming and outgoing frames; phase detector means for detecting a phase difference between said incoming and outgoing frames; and control means for sequentially writing signals on said incoming highway into an alternate one of said first and second time switch memories and sequentially reading signals from the other alternate one of said first and second time switch memories into the time slots of said outgoing highway in accordance with said phase difference and an interchanging relationship between signals on said incoming highway and corresponding signals on said outgoing highway so that the beginning of said outgoing frame coincides with the one of said time slots of said incoming frame which is displaced from the beginning of said incoming frame by an amount equal to said detected phase difference.

Claim 3

A time division switching system for multi-channel calls, comprising: an incoming highway (101) for supporting an incoming frame having time slots in which signals of said multi-channel calls are carried; an outgoing highway (108) for supporting an outgoing frame having time slots in which corresponding signals of said multi-channel calls are carried; first and second time switch memories (104,105) each having memory locations corresponding to the time slots of each of said incoming and outgoing frames; a frame detector (109) connected to said incoming highway for detecting the beginning of said incoming frame; means (110) for supplying a write address to said first and second time switch memories in synchronism with the time slots of said incoming frame; a demultiplexer (102) having an input terminal connected to said incoming highway and first and second output terminals connected respectively to input terminals of said first and second time switch memories, said demultiplexer switching said incoming highway between said first and second output terminals in the presence of a most significant bit of said write address; a multiplexer (106) having first and second input terminals connected respectively to output terminals of said first and second time switch memories and an output terminal connected to said outgoing highway, said multiplexer switching said outgoing highway between said first and second input terminals in the absence of said most significant bit of said write address; a control memory (121) having memory locations corresponding to the time slots of each of said incoming and outgoing frames; means (112) for generating a read address of said control memory in synchronism with the time slots of said outgoing frame; latch means (113) for latching said read address as an indication of a phase difference between said incoming and outgoing frames in response to an output signal from said frame detector; and control means (120) for writing a read address of said first and second time switch memories into said control memory in accordance with said latched address and a time slot interchanging relationship between said incoming and outgoing highways and reading the stored read address from said control memory into said first and second time switch memories in accordance with said read address of said control memory.

Claim 4

A time division switching system for multi-channel calls, comprising: an incoming highway (101) for supporting an incoming frame having time slots in which signals of said multi-channel calls are carried; an outgoing highway (108) for supporting an outgoing frame having time slots in which corresponding signals of said multi-channel calls are carried; first and second time switch memories (104,105) each having memory locations corresponding to the time slots of each of said incoming and outgoing frames; a frame detector (109) connected to said incoming highway for detecting the beginning of said incoming frame; means (110) for supplying a write address to said first and second time switch memories in synchronism with the time slots of said incoming frame; a demultiplexer (102) having an input terminal connected to said incoming highway and first and second output terminals connected respectively to input terminals of said first and second time switch memories, said demultiplexer switching said incoming highway between said first and second output terminals in the presence of a most significant bit of said write address; a multiplexer (106) having first and second input terminals connected respectively to output terminals of said first and second time switch memories and an output terminal connected to said outgoing highway, said multiplexer switching said outgoing highway between said first and second input terminals in the absence of said most significant bit of said write address; a control memory (121) having memory locations corresponding to the time slots of each of said incoming and outgoing frames; means (112) for generating a read address of said control memory in synchronism with the time slots of said outgoing frame; latch means (113) for latching said read address as an indication of a phase difference between said incoming and outgoing frames in response to an output signal from said frame detector; and control means (120) for writing a read address of said first and second time switch memories into said control memory in accordance with said latched address and a time slot interchanging relationship between said incoming and outgoing highways and reading the stored read address from said control memory into said first and second time switch memories in accordance with said read address of said control memory.

Claim 5

A time division switching system for multi-channel calls, comprising: an incoming highway (401) for supporting an incoming frame having time slots in which signals of said multi-channel calls are carried; an outgoing highway (408) for supporting an outgoing frame having time slots in which corresponding signals of said multi-channel calls are carried; first and second time switch memories (404,405) each having memory locations corresponding to the time slots of each of said incoming and outgoing frames; a frame detector (409) connected to said incoming highway for detecting the beginning of said incoming frame; means (410) for supplying a write address to said first and second time switch memories in synchronism with the time slots of said incoming frame; a control memory (421) having memory locations corresponding to the time slots of each of said incoming and outgoing frames; means (412) for generating a read address of said control memory in synchronism with the time slots of said outgoing frame; a demultiplexer (402) having an input terminal connected to said incoming highway (401) and first and second output terminals connected respectively to input terminals of said first and second time switch memories, said demultiplexer switching said incoming highway between said first and second output terminals in the presence of a most significant bit of said read address of said control memory; a multiplexer (406) having first and second input terminals connected respectively to output terminals of said first and second time switch memories and an output terminal connected to said outgoing highway, said multiplexer switching said outgoing highway between said first and second input terminals in the absence of said most significant bit of said read address of said control memory; latch means (413) for latching said write address of said first and second time switch memories as an indication of a phase difference between said incoming and outgoing frames in response to said most significant bit of said read address; and control means (420) for writing a read address of said first and second time switch memories into said control memory (421) in accordance with said latched address and a time slot interchanging relationship between said incoming and outgoing highways and reading the stored read address from said control memory into said first and second time switch memories in accordance with said read address of said control memory.

Claim 6

A time division switching system for multi-channel calls, comprising: an incoming highway (401) for supporting an incoming frame having time slots in which signals of said multi-channel calls are carried; an outgoing highway (408) for supporting an outgoing frame having time slots in which corresponding signals of said multi-channel calls are carried; first and second time switch memories (404,405) each having memory locations corresponding to the time slots of each of said incoming and outgoing frames; a frame detector (409) connected to said incoming highway for detecting the beginning of said incoming frame; means (410) for supplying a write address to said first and second time switch memories in synchronism with the time slots of said incoming frame; a control memory (421) having memory locations corresponding to the time slots of each of said incoming and outgoing frames; means (412) for generating a read address of said control memory in synchronism with the time slots of said outgoing frame; a demultiplexer (402) having an input terminal connected to said incoming highway (401) and first and second output terminals connected respectively to input terminals of said first and second time switch memories, said demultiplexer switching said incoming highway between said first and second output terminals in the presence of a most significant bit of said read address of said control memory; a multiplexer (406) having first and second input terminals connected respectively to output terminals of said first and second time switch memories and an output terminal connected to said outgoing highway, said multiplexer switching said outgoing highway between said first and second input terminals in the absence of said most significant bit of said read address of said control memory; latch means (413) for latching said write address of said first and second time switch memories as an indication of a phase difference between said incoming and outgoing frames in response to said most significant bit of said read address; and control means (420) for writing a read address of said first and second time switch memories into said control memory (421) in accordance with said latched address and a time slot interchanging relationship between said incoming and outgoing highways and reading the stored read address from said control memory into said first and second time switch memories in accordance with said read address of said control memory.

Claim 7

A time division switching system for multi-channel calls, comprising: an incoming highway for supporting a series of incoming frames having time slots in which signals of said multi-channel calls are contained; an outgoing highway for supporting a series of outgoing frames having time slots in which corresponding signals of said multi-channels calls are carried; first and second time switch memories each having memory locations corresponding to the time slots of each of said incoming and outgoing frames; phase detector means for detecting a phase difference between said incoming and outgoing frames; and control means for (a) sequentially writing signals on said incoming highway into an alternate one of said first and second time switch memories, (b) generating a first signal if a condition is satisfied which states that a signal of a given multi-channel call is located between the beginning of a first outgoing frame and the end of a first incoming frame which at least partially overlaps with the first outgoing frame and a corresponding outgoing signal is located between the beginning of a second, subsequent outgoing frame and the end of a second, subsequent incoming frame, or a second signal when said condition is not satisfied, and (c) sequentially reading all signals of said given multi-channel call from one of said first and second time switch memories into said second outgoing frame in accordance with said phase difference and a time slot interchanging relationship between said incoming and outgoing highways in the presence of said first signal and sequentially reading all signals of said given multi-channel call from one of said time switch memories into said first outgoing frame in accordance with said phase difference and said time slot interchanging relationship in the presence of said second signal.

Claim 8

A time division switching system for multi-channel calls, comprising: an incoming highway for supporting a series of incoming frames having time slots in which signals of said multi-channel calls are contained; an outgoing highway for supporting a series of outgoing frames having time slots in which corresponding signals of said multi-channels calls are carried; first and second time switch memories each having memory locations corresponding to the time slots of each of said incoming and outgoing frames; phase detector means for detecting a phase difference between said incoming and outgoing frames; and control means for (a) sequentially writing signals on said incoming highway into an alternate one of said first and second time switch memories, (b) generating a first signal if a condition is satisfied which states that a signal of a given multi-channel call is located between the beginning of a first outgoing frame and the end of a first incoming frame which at least partially overlaps with the first outgoing frame and a corresponding outgoing signal is located between the beginning of a second, subsequent outgoing frame and the end of a second, subsequent incoming frame, or a second signal when said condition is not satisfied, and (c) sequentially reading all signals of said given multi-channel call from one of said first and second time switch memories into said second outgoing frame in accordance with said phase difference and a time slot interchanging relationship between said incoming and outgoing highways in the presence of said first signal and sequentially reading all signals of said given multi-channel call from one of said time switch memories into said first outgoing frame in accordance with said phase difference and said time slot interchanging relationship in the presence of said second signal.

Claim 9

A time division switching system for multi-channel calls, comprising: an incoming highway (501) for supporting a series of incoming frames having time slots in which signals of said multi-channel calls are carried; an outgoing highway (508) for supporting a series of outgoing frames having time slots in which corresponding signals of said multi-channels calls are carried; first and second time switch memories (504,505) each having memory locations corresponding to the time slots of each of said incoming and outgoing frames; a frame detector (509) connected to said incoming highway for detecting the beginning of said incoming frame; means (510) for supplying a write address to said first and second time switch memories in synchronism with the time slots of said incoming frame; a demultiplexer (502) having an input terminal connected to said incoming highway and first and second output terminals connected respectively to input terminals of said first and second time switch memories, said demultiplexer switching said incoming highway between said first and second output terminals in the presence of a most significant bit of said write address; a control memory (521) having first and second memory locations corresponding to the time slots of each of said incoming and outgoing frames; means (512) for generating a read address of said control memory in synchronism with the time slots of said outgoing frame; latch means (513) for latching said read address as an indication of a phase difference between said incoming and outgoing frames in response to an output signal from said frame detector; and control means (520) responsive to said latched address and to a time slot interchanging relationship between said incoming and outgoing highways for (a₁) writing a read address of said first and second time switch memories into said first memory locations of said control memory, (a₂) writing a first binary signal into said second memory locations of said control memory if a condition is satisfied which states that a signal of a multi-channel call is located between the beginning of a first outgoing frame and the end of a first incoming frame which at least partially overlaps with the first outgoing frame and a corresponding outgoing signal is located beween the beginning of a second, subsequent outgoing frame and the end of a second, subsequent incoming frame, or a second signal when said condition is not satisfied, (a₃) writing a second binary signal into said second memory locations of said control memory if said condition is not satisfied, and (b) sequentially reading signals from said first and second memory locations of said control memory in accordance with said read address of said control memory; exclusive-OR gate means (511) for receiving said first and second binary signals from said control memory and a most significant bit of said read address of said control memory; and a multiplexer (506) having first and second input terminals connected respectively to output terminals of said first and second time switch memories and an output terminal connected to said outgoing highway, said multiplexer selectively switching said first and second input terminals to said outgoing highway in response to an output signal from said exclusive-OR gate means.

Claim 10

A time division switching system for multi-channel calls, comprising: an incoming highway (501) for supporting a series of incoming frames having time slots in which signals of said multi-channel calls are carried; an outgoing highway (508) for supporting a series of outgoing frames having time slots in which corresponding signals of said multi-channels calls are carried; first and second time switch memories (504,505) each having memory locations corresponding to the time slots of each of said incoming and outgoing frames; a frame detector (509) connected to said incoming highway for detecting the beginning of said incoming frame; means (510) for supplying a write address to said first and second time switch memories in synchronism with the time slots of said incoming frame; a demultiplexer (502) having an input terminal connected to said incoming highway and first and second output terminals connected respectively to input terminals of said first and second time switch memories, said demultiplexer switching said incoming highway between said first and second output terminals in the presence of a most significant bit of said write address; a control memory (521) having first and second memory locations corresponding to the time slots of each of said incoming and outgoing frames; means (512) for generating a read address of said control memory in synchronism with the time slots of said outgoing frame; latch means (513) for latching said read address as an indication of a phase difference between said incoming and outgoing frames in response to an output signal from said frame detector; and control means (520) responsive to said latched address and to a time slot interchanging relationship between said incoming and outgoing highways for (a₁) writing a read address of said first and second time switch memories into said first memory locations of said control memory, (a₂) writing a first binary signal into said second memory locations of said control memory if a condition is satisfied which states that a signal of a multi-channel call is located between the beginning of a first outgoing frame and the end of a first incoming frame which at least partially overlaps with the first outgoing frame and a corresponding outgoing signal is located beween the beginning of a second, subsequent outgoing frame and the end of a second, subsequent incoming frame, or a second signal when said condition is not satisfied, (a₃) writing a second binary signal into said second memory locations of said control memory if said condition is not satisfied, and (b) sequentially reading signals from said first and second memory locations of said control memory in accordance with said read address of said control memory; exclusive-OR gate means (511) for receiving said first and second binary signals from said control memory and a most significant bit of said read address of said control memory; and a multiplexer (506) having first and second input terminals connected respectively to output terminals of said first and second time switch memories and an output terminal connected to said outgoing highway, said multiplexer selectively switching said first and second input terminals to said outgoing highway in response to an output signal from said exclusive-OR gate means.

Claim 11

A time division switching sytem as claimed in claim 5, wherein said control means reverses the values of said first and second binary signals when said phase difference is greater than one-frame interval but smaller than two-frame interval.

Claim 12

A time division switching system for multi-channel calls, comprising: an incoming highway for supporting a series of incoming frames having time slots in which signals of said multi-channel calls are contained; an outgoing highway for supporting a series of outgoing frames having time slots in which corresponding signals of said multi-channels calls are carried; first and second time switch memories each having memory locations corresponding to the time slots of each of said incoming and outgoing frames; phase detector means for detecting a phase difference between said incoming and outgoing frames; control means for (a) sequentially writing signals on said incoming highway into an alternate one of first and second time switch memories, (b) generating a first signal when the time slot of at least one signal of a given multi-channel call of a given incoming frame is later than the time slot of a corresponding signal on a corresponding outgoing frame, or a second signal when the time slots of all signals of said multi-­channel call on said given incoming frame are earlier than the time slots of respectively corresponding signals on said corresponding outgoing frame, and (c) sequentially reading all signals of said given multi-channel call from one of said first and second time switch memories into an outgoing frame subsequent to said corresponding outgoing frame in accordance with said phase difference and a time slot interchanging relationship between said incoming and outgoing highways in the presence of said first signal and sequentially reading all signals of said given multi-channel call from one of said time switch memories into said corresponding outgoing frame in accordance with said phase difference and said time slot interchanging relationship in the presence of said second signal.

Claim 13

A time division switching system for multi-channel calls, comprising: an incoming highway for supporting a series of incoming frames having time slots in which signals of said multi-channel calls are contained; an outgoing highway for supporting a series of outgoing frames having time slots in which corresponding signals of said multi-channels calls are carried; first and second time switch memories each having memory locations corresponding to the time slots of each of said incoming and outgoing frames; phase detector means for detecting a phase difference between said incoming and outgoing frames; control means for (a) sequentially writing signals on said incoming highway into an alternate one of first and second time switch memories, (b) generating a first signal when the time slot of at least one signal of a given multi-channel call of a given incoming frame is later than the time slot of a corresponding signal on a corresponding outgoing frame, or a second signal when the time slots of all signals of said multi-­channel call on said given incoming frame are earlier than the time slots of respectively corresponding signals on said corresponding outgoing frame, and (c) sequentially reading all signals of said given multi-channel call from one of said first and second time switch memories into an outgoing frame subsequent to said corresponding outgoing frame in accordance with said phase difference and a time slot interchanging relationship between said incoming and outgoing highways in the presence of said first signal and sequentially reading all signals of said given multi-channel call from one of said time switch memories into said corresponding outgoing frame in accordance with said phase difference and said time slot interchanging relationship in the presence of said second signal.

Claim 14

A time division switching system for multi-channel calls, comprising: an incoming highway (501) for supporting a series of incoming frames having time slots in which signals of said multi-channel calls are carried; an outgoing highway (508) for supporting a series of outgoing frames having time slots in which corresponding signals of said multi-channels calls are carried; first and second time switch memories (504,505) each having memory locations corresponding to the time slots of each of said incoming and outgoing frames; a frame detector (509) connected to said incoming highway for detecting the beginning of said incoming frame; means (510) for supplying a write address to said first and second time switch memories in synchronism with the time slots of said incoming frame; a demultiplexer (502) having an input terminal connected to said incoming highway and first and second output terminals connected respectively to input terminals of said first and second time switch memories, said demultiplexer switching said incoming highway between said first and second output terminals in the presence of a most significant bit of said write address; a control memory (521) having first and second memory locations corresponding to the time slots of each of said incoming and outgoing frames; means (512) for generating a read address of said control memory in synchronism with the time slots of said outgoing frame; latch means (513) for latching said read address as an indication of a phase difference between said incoming and outgoing frames in response to an output signal from said frame detector; and control means (520) responsive to said latched address and to a time slot interchanging relationship between said incoming and outgoing highways for (a₁) writing a read address of said first and second time switch memories into said first memory locations of said control memory, (a₂) writing a first binary signal into said second memory locations of said control memory if the time slot of at least one signal of a given multi-channel call on a given incoming frame is later than the time slot of a corresponding signal of a corresponding outgoing frame, (a₃) writing a second binary signal into said second memory locations of said control memory when the time slots of all signals of said given multi-channel call on said given incoming frame are earlier than the time slots of respectively corresponding signals on said corresponding outgoing frame, and (b) sequentially reading signals from said first and second memory locations of said control memory in accordance with said read address of said control memory; exclusive-OR gate means (511) for receiving said first and second binary signals from said control memory and a most significant bit of said read address of said control memory; and a multiplexer (506) having first and second input terminals connected respectively to output terminals of said first and second time switch memories and an output terminal connected to said outgoing highway, said multiplexer selectively switching said first and second input terminals to said outgoing highway in response to an output signal from said exclusive-OR gate means.

Claim 15

A time division switching system for multi-channel calls, comprising: an incoming highway (501) for supporting a series of incoming frames having time slots in which signals of said multi-channel calls are carried; an outgoing highway (508) for supporting a series of outgoing frames having time slots in which corresponding signals of said multi-channels calls are carried; first and second time switch memories (504,505) each having memory locations corresponding to the time slots of each of said incoming and outgoing frames; a frame detector (509) connected to said incoming highway for detecting the beginning of said incoming frame; means (510) for supplying a write address to said first and second time switch memories in synchronism with the time slots of said incoming frame; a demultiplexer (502) having an input terminal connected to said incoming highway and first and second output terminals connected respectively to input terminals of said first and second time switch memories, said demultiplexer switching said incoming highway between said first and second output terminals in the presence of a most significant bit of said write address; a control memory (521) having first and second memory locations corresponding to the time slots of each of said incoming and outgoing frames; means (512) for generating a read address of said control memory in synchronism with the time slots of said outgoing frame; latch means (513) for latching said read address as an indication of a phase difference between said incoming and outgoing frames in response to an output signal from said frame detector; and control means (520) responsive to said latched address and to a time slot interchanging relationship between said incoming and outgoing highways for (a₁) writing a read address of said first and second time switch memories into said first memory locations of said control memory, (a₂) writing a first binary signal into said second memory locations of said control memory if the time slot of at least one signal of a given multi-channel call on a given incoming frame is later than the time slot of a corresponding signal of a corresponding outgoing frame, (a₃) writing a second binary signal into said second memory locations of said control memory when the time slots of all signals of said given multi-channel call on said given incoming frame are earlier than the time slots of respectively corresponding signals on said corresponding outgoing frame, and (b) sequentially reading signals from said first and second memory locations of said control memory in accordance with said read address of said control memory; exclusive-OR gate means (511) for receiving said first and second binary signals from said control memory and a most significant bit of said read address of said control memory; and a multiplexer (506) having first and second input terminals connected respectively to output terminals of said first and second time switch memories and an output terminal connected to said outgoing highway, said multiplexer selectively switching said first and second input terminals to said outgoing highway in response to an output signal from said exclusive-OR gate means.

Claim 16

A time division switching system as claimed in claim 8, wherein said control means reverses the values of said first and second binary signals when said phase difference is greater than one frame interval but smaller than two-frame interval.