EP0325419A2
Expired / Lapsed
EP
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Method and apparatus for caching interlock variables in an integrated cache memory
Assignee: Advanced Micro Devices Inc
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Filing: 1989-01-18
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Granted: —
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Expires: 2009-01-18
Abstract
Abstract Methods and apparatus are disclosed for supporting the caching of interlock variables in cache memory units employed in multiprocessor and/or multitasking environments. The preferred embodiment of the invention includes methods and apparatus for selectively treating interlock variables as cachable or non-cachable. The disclosed methods and apparatus are suitable for supporting high speed data and instruction processing applications in both RISC and non-RISC architecture environments, can be integrated on a single chip and allows for better performance and utilization of the computer system bus structure since most of the interlock variable accesses are faster and do not appear on the memory bus (only in the cache).
Inventors
- 👤 Gigy Baror
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 17:31
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0888; G06F12/0806; G06F12/0815; G06F12/0837; G06F12/0844; G06F12/0846; G06F12/0848; G06F15/00; G06F15/76; G06F15/78; G06F15/7828; G06F15/7835
Claims Analysis
Total Claims: 40
Claim 1
Independent Claim
149 words
An integrated cache unit ("ICU") architecture that supports the caching of interlock variables along with the implementation of other cache functions, in a computing system, wherein said system includes at least one central processing unit ("CPU"), processor bus means which facilitate communication between said CPU and the ICU, memory and memory bus means which facilitate communication between said memory and the ICU, comprising: (a) a processor bus unit, coupled to said processor bus means, for controlling an ICU/processor bus interface; (b) a memory bus unit, coupled to said memory bus means, for controlling an ICU/memory bus interface; and (c) a programmable cache unit, coupled to both said processor bus unit, and said memory bus unit, for performing cache functions, wherein said programmable cache unit includes a set of special registers for selecting programmable options including a cache interlock enable option which, when selected, permits the caching of interlock variables.
Claim 2
Dependent Claim
149 words
An integrated cache unit ("ICU") architecture that supports the caching of interlock variables along with the implementation of other cache functions, in a computing system, wherein said system includes at least one central processing unit ("CPU"), processor bus means which facilitate communication between said CPU and the ICU, memory and memory bus means which facilitate communication between said memory and the ICU, comprising: (a) a processor bus unit, coupled to said processor bus means, for controlling an ICU/processor bus interface; (b) a memory bus unit, coupled to said memory bus means, for controlling an ICU/memory bus interface; and (c) a programmable cache unit, coupled to both said processor bus unit, and said memory bus unit, for performing cache functions, wherein said programmable cache unit includes a set of special registers for selecting programmable options including a cache interlock enable option which, when selected, permits the caching of interlock variables.
Claim 3
Dependent Claim
45 words
An ICU architecture as set forth in claim 1 wherein said programmable cache unit is associated with memory array means which, in a first configuration is located within said programmable cache means and which, in a second configuration, is located outside said programmable cache means.
Claim 4
Dependent Claim
38 words
An ICU architecture as set forth in claim 2 wherein said memory array means stores cached data and instruction signals and is organized as a set of blocks, each block corresponding to a predetermined number of cached words.
Claim 5
Dependent Claim
20 words
An ICU architecture as set forth in claim 3 wherein said programmable cache unit supports variable block and sub-block sizing.
Claim 6
Dependent Claim
121 words
An ICU architecture as set forth in claim 3 wherein said programmable cache unit further comprises: (a) a cache unit address bus, coupled to said processor bus unit and said memory bus unit, for carrying address signals; (b) a cache unit data bus, coupled to said processor bus unit and said memory bus unit, for carrying data signals; (c) block status array means coupled to said cache data bus, for storing an indication of the modified, shared and locked status of each block; and (d) cache unit control means, coupled to said processor bus control means and said memory bus control means, for synchronizing and controlling operations of said programmable cache unit, said processor bus unit and said memory bus unit.
Claim 7
Dependent Claim
42 words
An ICU arthitecture as set forth in claim 5 wherein said cache control means is further operative to generate hit signals for valid cache accesses and maintains and updates data stored in said set of special registers and said block status array.
Claim 8
Dependent Claim
29 words
An ICU arthitecture as set forth in claim 6 further comprising means operative to treat interlock variables as non-cachable whenever said cache interlock enable option has not been selected.
Claim 9
Dependent Claim
34 words
An ICU architecture as set forth in claim 7 further comprising means for transferring any access to an interlock variable to said memory bus with a lock indication whenever said interlock variables are non-cachable.
Claim 10
Dependent Claim
22 words
An ICU architecture as set forth in claim 6 further comprising means for indicating that a processor access is an interlocked access.
Claim 11
Dependent Claim
28 words
An ICU architecture as set forth in claim 9 further comprising means, coupled to said memory bus interface, for indicating that a memory access is an interlocked access.
Claim 12
Dependent Claim
27 words
An ICU architecture as set forth in claim 10 further comprising means for locking a variable for exclusive use of a specified processor in a multiprocessor environment.
Claim 13
Dependent Claim
47 words
An ICU architecture as set forth in claim 11 wherein said set of special registers includes at least one programmable register having at least one bit for selecting a 2 n way set associative cache organization where n is an integer greater than or equal to zero.
Claim 14
Dependent Claim
16 words
An ICU architecture as set forth in claim 6 further comprising means for testing interlocked variables.
Claim 15
Dependent Claim
64 words
An ICU architecture as set forth in claim 13 which, whenever said cache enable option is selected and no hit occurs in a shared block, is operative to treat an interlocked read as a miss, starts a reload operation on said memory bus, generates a lock indication signal and stores the read data in a cache memory block which is thereafter assigned as shared.
Claim 16
Dependent Claim
35 words
An ICU architecture as set forth in claim 14 which is operative, whenever an interlocked read occurs with a hit in a shared block, to supply data from the cache with no memory bus access.
Claim 17
Dependent Claim
49 words
An ICU architecture as set forth in claim 14 which, whenever said cache enable option is selected, is operative to treat an interlocked write operation as a function of the state of a processor generated lock indication signal input by said processor in the cycle preceeding the write access.
Claim 18
Dependent Claim
30 words
An ICU architecture as set forth in claim 16 which, whenever said lock indication signal is in a first state, is operative to initiate a write-through operation to said memory.
Claim 19
Dependent Claim
30 words
An ICU architecture as set forth in claim 17 which, whenever said lock indication signal is in a second state, is operative to write data into said memory array means.
Claim 20
Dependent Claim
47 words
An ICU architecture as set forth in claim 18 which is further operative to write data to said memory, if a prior read access generated a miss, in order to guarantee that the memory will be written only the first time that the interlocked variable is read.
Claim 21
Dependent Claim
25 words
An ICU architecture as set forth in claim 19 further comprising means for asserting a lock indication signal to said memory during memory write operations.
Claim 22
Dependent Claim
20 words
An ICU architecture as set forth in claim 20 that is integrated on a single chip, is modular and expandable.
Claim 23
Dependent Claim
21 words
An ICU architecture as set forth in claim 13 wherein the ICU is capable of being operated as a cache master.
Claim 24
Dependent Claim
36 words
An ICU architecture as set forth in claim 22 wherein an ICU cache master outputs a signal via said shared means for indicating memory bus accesses, whenever an interlocked access is presented on said memory bus.
Claim 25
Dependent Claim
16 words
An ICU architecture as set forth in claim 23 further comprising means for releasing interlocked variables.
Claim 26
Dependent Claim
48 words
An ICU architecture as set forth in claim 24 wherein said means for releasing an interlocked variable further comprises means for invalidating cache variables to assure subsequent processor accesses will be a miss and assure the most up to date value of the variable is read from memory.
Claim 27
Dependent Claim
20 words
An ICU architecture as set forth in claim 25 that is integrated on a single chip, is modular and expandable.
Claim 28
Independent Claim
167 words
A method for caching interlock variables in an integrated cache unit ("ICU") architecture that supports other cache functions in a computing system, wherein said system includes at least one central processing unit ("CPU"), processor bus means which facilitate communication between said CPU and the ICU, memory and memory bus means which facilitate communication between said memory and the ICU, comprising the steps of: (a) controlling an ICU/processor bus interface from within said ICU utilizing a processor bus unit coupled to said processor bus means; (b) controlling an ICU/memory bus interface from within said ICU utilizing a memory bus unit coupled to said memory bus means; and (c) performing cache functions from within said ICU utilizing a programmable cache unit coupled to both said processor bus unit and said memory bus unit, wherein said programmable cache unit includes a set of special registers for selecting programmable options including a cache interlock enable option which, when selected, permits the caching of interlock variables in an associated memory array means.
Claim 29
Independent Claim
167 words
A method for caching interlock variables in an integrated cache unit ("ICU") architecture that supports other cache functions in a computing system, wherein said system includes at least one central processing unit ("CPU"), processor bus means which facilitate communication between said CPU and the ICU, memory and memory bus means which facilitate communication between said memory and the ICU, comprising the steps of: (a) controlling an ICU/processor bus interface from within said ICU utilizing a processor bus unit coupled to said processor bus means; (b) controlling an ICU/memory bus interface from within said ICU utilizing a memory bus unit coupled to said memory bus means; and (c) performing cache functions from within said ICU utilizing a programmable cache unit coupled to both said processor bus unit and said memory bus unit, wherein said programmable cache unit includes a set of special registers for selecting programmable options including a cache interlock enable option which, when selected, permits the caching of interlock variables in an associated memory array means.
Claim 30
Dependent Claim
124 words
A method as set forth in claim 27 wherein said step of performing cache functions utilizing a programmable cache unit further comprises the steps of: (a) carrying address signals within said ICU on an internal cache unit address bus coupled to said processor bus unit and said memory bus unit; (b) carrying data signals within said ICU on an internal cache unit data bus coupled to said processor bus unit and said memory bus unit; (c) storing an indication of the modified, shared and locked status of each block in block status array means coupled to said cache data bus; and (d) synchronizing and controlling operations of said programmable cache unit, said processor bus and said memory bus unit via cache unit control means.
Claim 31
Dependent Claim
42 words
A method as set forth in claim 28 further comprising the steps of generating hit signals for valid cache accesses and maintaining and updating data stored in said set of special registers and said block status array, via said cache control means.
Claim 32
Dependent Claim
28 words
A method as set forth in claim 29 further comprising the step of treating interlock variables as non-cachable whenever said cache interlock enable option has not been selected.
Claim 33
Dependent Claim
36 words
A method as set forth in claim 30 further comprising the steps of transferring any access to an interlock variable to said memory bus and generating a lock indication signal whenever said interlock variables are non-cachable.
Claim 34
Dependent Claim
25 words
A method as set forth in claim 30 further comprising the step of generating a first signal whenever a processor access is an interlocked access.
Claim 35
Dependent Claim
25 words
A method as set forth in claim 32 further comprising the step of generating a second signal whenever a memory access is an interlocked access.
Claim 36
Dependent Claim
27 words
A method as set forth in claim 33 further comprising the step of locking a variable for exclusive use of a specified processor in a multiprocessor environment.
Claim 37
Dependent Claim
15 words
A method as set forth in claim 29 further comprising means for testing interlocked variables.
Claim 38
Dependent Claim
70 words
A method as set forth in claim 35 which, whenever said cache enable option is selected and no hit occurs in a shared block, further comprises the steps of: (a) treating an interlocked read as a miss; (b) starting a reload operation on said memory bus; (c) generating a lock indication signal; and (d) storing the read data in a cache memory array block which is thereafter assigned as shared.
Claim 39
Dependent Claim
38 words
A method as set forth in claim 36 which, whenever an interlocked read occurs with a hit in a shared block, further comprises the step of supplying data from the cache memory array with no memory bus access.
Claim 40
Dependent Claim
50 words
A method as set forth in claim 36 which, whenever said cache enable option is selected, further comprises the step of treating an interlocked write operation as a function of the state of a processor generated lock indication signal input by said processor in the cycle preceeding the write access.
References Cited (Backward Citations)
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