EP0340720A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Interface circuit
Assignee: Toshiba Corp
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Filing: 1989-05-02
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Granted: —
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Expires: 2009-05-02
Abstract
Abstract An interface circuit includes a power source terminal (VDD), an input terminal (IN) and NPN transistor (Q11). The interface circuit further includes a first resistor (R11) connected between the emitter of the NPN transistor (Q11) and the input terminal (IN), a second resistor (R14) connected between the collector of the NPN transistor (Q11) and the power source terminal (VDD) a diode (D1) connected in a forward direction between the collector of the NPN transistor (Q11) and the power source terminal (VDD) and a voltage dividing circuit (R12, R13) for biasing the base of the NPN transistor (Q11) to a preset potential.
Inventors
- 👤 Michinori Intellectual Property Division Nakamura
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-24 13:48
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/018; H03K19/01806
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
111 words
An interface circuit comprising: an input terminal (IN); a power source terminal (VDD) set at a positive potential; and an NPN transistor (Q11) having a base, a collector and an emitter; characterized by further comprising first resistor means (R11) connected between the emitter of said NPN transistor (Q11) and said input terminal (IN), second resistor means (R14) connected between the collector of said NPN transistor (Q11) and said power source terminal (VDD), diode means (D1) connected in forward direction between the collector of said NPN transistor (Q11) and said power source terminal (VDD), and bias means (R12, R13) for biasing the base of said NPN transistor (Q11) to a preset potential.
Claim 2
Dependent Claim
111 words
An interface circuit comprising: an input terminal (IN); a power source terminal (VDD) set at a positive potential; and an NPN transistor (Q11) having a base, a collector and an emitter; characterized by further comprising first resistor means (R11) connected between the emitter of said NPN transistor (Q11) and said input terminal (IN), second resistor means (R14) connected between the collector of said NPN transistor (Q11) and said power source terminal (VDD), diode means (D1) connected in forward direction between the collector of said NPN transistor (Q11) and said power source terminal (VDD), and bias means (R12, R13) for biasing the base of said NPN transistor (Q11) to a preset potential.
Claim 3
Dependent Claim
24 words
An interface circuit according to claim 1, characterized in that the emitter of said NPN transistor (Q11) is grounded via third resistor means (R21).
Claim 4
Dependent Claim
51 words
An interface circuit according to claim 2, characterized by further comprising switching means (M11) formed in an IC chip different from an IC chip in which said input terminal (IN), power source terminal (VDD), diode means (D1) and bias means (R12, R13) are formed, for selectively grounding said input terminal (IN).
Claim 5
Dependent Claim
21 words
An interface circuit according to claim 3, characterized in that said switching means is an opendrain output type MOS transistor (M11).
Claim 6
Dependent Claim
29 words
An interface circuit according to claim 4, characterized in that said bias means includes a voltage divider (R12, R13) for dividing the potential of said power source terminal (VDD).
Claim 7
Dependent Claim
67 words
An interface circuit according to claim 5, characterized in that said voltage divider includes fourth resistor means (R13) grounded at one end and fifth resistor means (R12) connected between the other end of said fourth resistor means (R13) and said power source terminal (VDD), and the base of said NPN transistor (Q11) is connected to a connection node between said fourth and fifth resistor means (R12, R13).
Claim 8
Dependent Claim
62 words
An interface circuit according to claim 1, characterized by further comprising switching means (M11) formed in an IC chip different from an IC chip in which said input terminal (IN), power source terminal (VDD), NPN transistor (Q11), first resistor means (R11), second resistor means (R14), diode means (D1) and bias means (R12, R13) are formed, for selectively grounding said input terminal (IN).
References Cited (Backward Citations)
No citation records indexed.
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