EP0341896A2
Expired / Lapsed
EP
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Content addressable memory array
Assignee: Advanced Micro Devices Inc
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Filing: 1989-05-04
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Granted: —
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Expires: 2009-05-04
Abstract
Abstract A content addressable memory system includes an array of memory cells arranged in rows and columns in an array of N bit cells by M words, with N bits per word, an I/O bus having a bit capacity S which is a submultiple of N, a mode generator for generating a plurality of commands, the commands including a command write command, a data write command, a data read command, and a status read command, the command write and the status read commands being encodable in S bits or less, and multiplexing means for supplying selected ones of the commands to the I/O bus.
Inventors
- 👤 Patrick T. Chuang
- 👤 Robert L. Yau
- 👤 Hiroshi Yoshida
- 👤 Moon-Yee Wang
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 21:10
CPC Classifications
G; G06; G06F; G06F16/00; G06F16/90; G06F16/903; G06F16/90335; G06F16/90339
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
102 words
A content addressable memory system comprising: an array of memory cells arranged in rows and columns in an array of N bit cells by M words, with N bits per word; an I/O bus having a bit capacity S which is a submultiple of N; a mode generator for generating a plurality of commands, said commands including a command write command, a data write command, a data read command,and a status read command, said command write and said status read commands being encodable in S bits or less; and multiplexing means for supplying selected ones of said commands to said I/O bus.
Claim 2
Dependent Claim
102 words
A content addressable memory system comprising: an array of memory cells arranged in rows and columns in an array of N bit cells by M words, with N bits per word; an I/O bus having a bit capacity S which is a submultiple of N; a mode generator for generating a plurality of commands, said commands including a command write command, a data write command, a data read command,and a status read command, said command write and said status read commands being encodable in S bits or less; and multiplexing means for supplying selected ones of said commands to said I/O bus.
Claim 3
Dependent Claim
43 words
A system in accordance with Claim 1 including a status register; means for supplying said status read command to said status register; and means for supplying status information from said status register to said I/O bus in response to said status read command.
Claim 4
Dependent Claim
58 words
A system in accordance with Claim 1 including an operation code generator connected to said I/O bus for generating one of a plurality of operation codes identifying different operations to be performed in said system; means for supplying said command write command to said operation code generator to cause said generator to generate one of said operation codes.
Claim 5
Dependent Claim
59 words
A system in accordance with Claim 2 including means for detecting the fill condition of said array of memory cells; means for supplying an indication of said fill condition of said array to said status register; and means for supplying said fill condition indication from said status register to said I/O bus in response to said status read command.
Claim 6
Dependent Claim
74 words
A system in accordance with Claim 2 including: means for conducting a search in said array to detect matches between one or more of said words in said array and words supplied to said search conducting means; means for supplying to said status register an indication of detection of a match; and means for supplying said match detection indication from said status register to said I/O bus in response to said status read command.
Claim 7
Dependent Claim
26 words
A system in accordance with Claim 5 including means for supplying to said status register an indication of the detection of multiple match in said words.
References Cited (Backward Citations)
No citation records indexed.
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