Improved method of planarization of topologies in integrated circuit structures

Claim 1

A method of making a highly planarized inte­grated circuit structure having highly planarized oxide portions using deposited oxide which is plan­arized to the level of adjacent portions of the integrated circuit structure which comprises: (a) depositing over an integrated circuit structure having first portions at a height higher than the remainder of said integrated circuit structure, a conformal oxide layer having a thickness which exceeds the height of said first portions above the remainder of said substrate; (b) depositing a layer of a planarizing material over said deposited oxide layer; (c) polishing said structure to expose the highest portions of said underlying conformal oxide layer; (d) etching said structure in a first etching step with an etchant system capable of remov­ing said conformal oxide layer selectively with respect to said layer of planarizing material to remove a portion of said conformal oxide layer; (e) polishing said structure again to remove the remainder of said planarizing material; and (f) etching the remainder of said structure in a second etching step until all of the oxide over said raised portions is removed leaving a highly planarized structure having oxide regions formed therein between said raised portions of said integrated circuit structure with the upper surface of said oxide regions substantially level with the upper surface of said raised portions of said inte­grated circuit structure.

Claim 2

A method of making a highly planarized inte­grated circuit structure having highly planarized oxide portions using deposited oxide which is plan­arized to the level of adjacent portions of the integrated circuit structure which comprises: (a) depositing over an integrated circuit structure having first portions at a height higher than the remainder of said integrated circuit structure, a conformal oxide layer having a thickness which exceeds the height of said first portions above the remainder of said substrate; (b) depositing a layer of a planarizing material over said deposited oxide layer; (c) polishing said structure to expose the highest portions of said underlying conformal oxide layer; (d) etching said structure in a first etching step with an etchant system capable of remov­ing said conformal oxide layer selectively with respect to said layer of planarizing material to remove a portion of said conformal oxide layer; (e) polishing said structure again to remove the remainder of said planarizing material; and (f) etching the remainder of said structure in a second etching step until all of the oxide over said raised portions is removed leaving a highly planarized structure having oxide regions formed therein between said raised portions of said integrated circuit structure with the upper surface of said oxide regions substantially level with the upper surface of said raised portions of said inte­grated circuit structure.

Claim 16

A method of making a highly planarized inte­grated circuit structure having field oxide regions formed therein between active regions of a sub­strate, and at the same level as the active reg­ions, which comprises: (a) patterning a silicon substrate with a mask having openings therein conforming to desired formation of field oxide regions in said substrate; (b) etching said silicon substrate through said mask to a depth of from about 0.45 mi­crons to about 0.55 microns; (c) removing said mask; (d) depositing from about 7000 to about 9000 Angstroms of a conformal oxide layer over said structure; (e) depositing a further layer of a planariz­ing material over said conformal oxide layer; (f) mechanically polishing said structure a first time to expose the highest portions of said underlying conformal oxide layer; (g) etching said structure a first time with an etchant system capable of removing said deposited conformal oxide and said layer of planarizing material at a oxide:planarizing material removal rate of at least about 8:1 until about 0.5 microns of said conformal oxide layer has been removed; (h) polishing said structure a second time to remove substantially all of said planarizing material left on said structure after said first etching step; (i) etching said structure a second time with an etchant system capable of removing any remaining portions of said planarizing mater­ial at about the same rate as said oxide until all of said planarizing material is removed; and (j) etching the remainder of said structure with an etchant which will etch oxide at a faster rate than silicon until all of said conformal oxide over said active regions is removed leaving a highly planarized structure having field oxide regions formed therein between active regions in the substrate with the upper surface of the field oxide regions substantially level with the surface of the active regions.

Claim 17

A method of making a highly planarized inte­grated circuit structure having field oxide regions formed therein between active regions of a sub­strate, and at the same level as the active reg­ions, which comprises: (a) patterning a silicon substrate with a mask having openings therein conforming to desired formation of field oxide regions in said substrate; (b) etching said silicon substrate through said mask to a depth of from about 0.45 mi­crons to about 0.55 microns; (c) removing said mask; (d) depositing from about 7000 to about 9000 Angstroms of a conformal oxide layer over said structure; (e) depositing a further layer of a planariz­ing material over said conformal oxide layer; (f) mechanically polishing said structure a first time to expose the highest portions of said underlying conformal oxide layer; (g) etching said structure a first time with an etchant system capable of removing said deposited conformal oxide and said layer of planarizing material at a oxide:planarizing material removal rate of at least about 8:1 until about 0.5 microns of said conformal oxide layer has been removed; (h) polishing said structure a second time to remove substantially all of said planarizing material left on said structure after said first etching step; (i) etching said structure a second time with an etchant system capable of removing any remaining portions of said planarizing mater­ial at about the same rate as said oxide until all of said planarizing material is removed; and (j) etching the remainder of said structure with an etchant which will etch oxide at a faster rate than silicon until all of said conformal oxide over said active regions is removed leaving a highly planarized structure having field oxide regions formed therein between active regions in the substrate with the upper surface of the field oxide regions substantially level with the surface of the active regions.

Claim 21

A method of making a highly planarized inte­grated circuit structure having a raised pattern thereon, which comprises: (a) forming a raised pattern on an integrated circuit structure; (b) depositing, at a temperature which will not damage said raised pattern, a conformal oxide layer over said raised pattern having a thickness sufficient, at its lowest point, to exceed the height of said raised pattern; (c) depositing, at a temperature which will not damage said raised pattern, a layer of planarizing material over said conformal oxide layer; (d) polishing said planarizing layer until the highest level of the underlying conformal oxide is exposed; (e) etching said conformal oxide/planarizing layers with an etchant which will remove said oxide at at least about 5 times the rate of removal of said planarizing material until the level of said oxide in areas exposed during said polishing step is reduced by an amount approximately equal to the thickness of said raised pattern; and (f) polishing said structure in a second polishing step to remove all of the remainder of said planarizing material from said struc­ture and form a highly planarized surface over said integrated circuit structure.

Claim 22

A method of making a highly planarized inte­grated circuit structure having a raised pattern thereon, which comprises: (a) forming a raised pattern on an integrated circuit structure; (b) depositing, at a temperature which will not damage said raised pattern, a conformal oxide layer over said raised pattern having a thickness sufficient, at its lowest point, to exceed the height of said raised pattern; (c) depositing, at a temperature which will not damage said raised pattern, a layer of planarizing material over said conformal oxide layer; (d) polishing said planarizing layer until the highest level of the underlying conformal oxide is exposed; (e) etching said conformal oxide/planarizing layers with an etchant which will remove said oxide at at least about 5 times the rate of removal of said planarizing material until the level of said oxide in areas exposed during said polishing step is reduced by an amount approximately equal to the thickness of said raised pattern; and (f) polishing said structure in a second polishing step to remove all of the remainder of said planarizing material from said struc­ture and form a highly planarized surface over said integrated circuit structure.