Semiconductor integrated circuit having a CMOS inverter

Claim 2

A semiconductor integrated circuit having a complementary metal oxide semiconductor (CMOS) inverter, including CMOS inverter means (32) having input and output terminals (IN, OUT), for inverting an input signal (Vin) applied to said input terminal to thereby output an output signal (Vout) through said output terminal, characterized by comprising means (Q3, Q4), connected to said CMOS inverter means, for rapidly passing a current (I) supplied from said CMOS inverter to a low-potential power source until a potential of said output terminal decreases to a predetermined potential in response to an increase in potential of said input signal and for slowly passing said current after the potential of said output terminal reaches said predetermined potential.

Claim 3

A semiconductor integrated circuit as claimed in claim 1, characterized in that said CMOS inverter means (32) has high and low threshold potentials defining logical values, and said predetermined potential is selected in the vicinity of said low threshold level and is slightly higher than said low threshold level.

Claim 4

A semiconductor integrated circuit as claimed in any of claims 1 and 2, characterized in that said means comprises first transistor means (Q3) for passing the current (I) supplied from said CMOS inverter means (32) by being held ON during the time when said input signal (Vin) increases, and second transistor means (Q4) for passing the current supplied from said CMOS inverter means by being held ON until the potential of said output terminal decreases to said predetermined potential and for stopping passing said current by being turned OFF after the potential of said output terminal reaches said predetermined potential.

Claim 5

A semiconductor integrated circuit as claimed in claim 3, characterized in that said second transistor means (Q4) has a driveability higher than that of said first transistor means (Q3).

Claim 6

A semiconductor integrated circuit as claimed in claim 3 or 4, characterized in that said CMOS inverter means (32) includes a P-channel MOS transistor (Q1) and an N-channel MOS transistor (Q2), and said N-channel MOS transistor has a driveability higher than that of said first transistor means (Q3).

Claim 7

A semiconductor integrated circuit as claimed in any of claims 3 to 5, characterized in that said first transistor means (Q3) includes a plurality of MOS transistors (Q3-1, Q3-2) connected in series.

Claim 8

A semiconductor integrated circuit as claimed in any of claims 3 to 6, characterized in that said second transistor means (Q4) includes a plurality of MOS transistors (Q4-1, Q4-2) connected in parallel.

Claim 9

A semiconductor integrated circuit as claimed in any of claims 1 to 7, characterized in that said circuit forms an output buffer (31).

Claim 10

A semiconductor integrated circuit having a complementary metal oxide semiconductor (CMOS) inverter, comprising a CMOS inverter (32) including a first P-channel MOS transistor (Q1) having a drain, source and gate, and a first N-channel MOS transistor (Q2) having a drain, source and gate, the source of said first P-channel MOS transistor being connected to a high-potential power source (V DD ) and forming an output of said circuit, the gates of said first P-channel and N-channel MOS transistors being mutually connected and supplied with an input signal, characterized by comprising a second N-channel MOS transistor (Q3) having a drain, source and gate, the drain of said second N-channel MOS transistor being connected to the source of said first N-channel MOS transistor, the source of said second N-channel MOS transistor being connected to a low-potential power source (V SS ), the gate of said second N-channel MOS transistor being connected to the gates of said first P-channel and N-channel MOS transistors, and a third N-channel MOS transistor (Q4) having a drain, source and gate, the drain of said third N-channel MOS transistor being connected to the source of said first N-channel MOS transistor, the source of said third N-channel MOS transistor being connected to said low-potential power source, the gate of said third N-channel MOS transistor being connected to said output of the circuit.

Claim 11

A semiconductor integrated circuit having a complementary metal oxide semiconductor (CMOS) inverter, comprising a CMOS inverter (32) including a first P-channel MOS transistor (Q1) having a drain, source and gate, and a first N-channel MOS transistor (Q2) having a drain, source and gate, the source of said first P-channel MOS transistor being connected to a high-potential power source (V DD ) and forming an output of said circuit, the gates of said first P-channel and N-channel MOS transistors being mutually connected and supplied with an input signal, characterized by comprising a second N-channel MOS transistor (Q3) having a drain, source and gate, the drain of said second N-channel MOS transistor being connected to the source of said first N-channel MOS transistor, the source of said second N-channel MOS transistor being connected to a low-potential power source (V SS ), the gate of said second N-channel MOS transistor being connected to the gates of said first P-channel and N-channel MOS transistors, and a third N-channel MOS transistor (Q4) having a drain, source and gate, the drain of said third N-channel MOS transistor being connected to the source of said first N-channel MOS transistor, the source of said third N-channel MOS transistor being connected to said low-potential power source, the gate of said third N-channel MOS transistor being connected to said output of the circuit.

Claim 12

A semiconductor integrated circuit as claimed in claim 9, characterized in that said third N-channel MOS transistor (Q4) has a driveability higher than that of said second N-channel MOS transistor (Q3).

Claim 13

A semiconductor integrated circuit as claimed in claim 9 or 10, characterized in that said first N-channel MOS transistor (Q2) has a driveability higher than that of said second N-channel MOS transistor (Q3).

Claim 14

A semiconductor integrated circuit as claimed in any of claims 9 to 11, characterized in that said second and third N-channel MOS transistors (Q3, Q4) form as a ringing noise reduction circuit.