Semiconductor memory device provided with low-noise power supply structure

Claim 2

A semiconductor memory device comprising a memory cell array having a plurality of memory cells, a first voltage terminal for receiving a first voltage, a first peripheral circuit operatively selecting at least one of said memory cells, a second peripheral circuit for operatively reading out a signal from the selected memory cell, an impedance element, a first power wiring for connecting said first peripheral circuit to said first voltage terminal without through said impedance element, and a second power wiring for connecting said impedance element between said second peripheral circuit and said first voltage terminal thereby to supply said second peripheral circuit with said first voltage through said impedance element.

Claim 3

The semiconductor memory device according to claim 1, in which each of said memory cells is a read-only memory cell.

Claim 4

The semiconductor memory device according to claim 1, further comprising a second voltage terminal for receiving a second voltage different from said first voltage, a third power wiring for connecting said first peripheral circuit to said second voltage terminal, and a fourth power wiring for connecting said second peripheral circuit to said second voltage terminal.

Claim 5

The semiconductor memory device according to claim 1, in which said second peripheral circuit includes a sense amplifier circuit for operatively amplifying a signal from the selected memory cell.

Claim 6

A read-only semiconducto memory device comprising: a memory cell array formed of a plurality of memory cell blocks arranged in a matrix form of rows and columns, each of said memory blocks having a series circuit of a plurality of memory cells; a plurality of column lines for connecting said memory cell blocks in the column direction; a plurality of row lines for connecting said memory cells forming said memory cell blocks in the row direction; a column selection circuit having a column decoder for receiving column address signals and a column selector driven by the output of said column decoder for selecting said column lines; a row selection circuit for receiving row address signals and selecting said row lines; a memory cell block selection circuit for receiving address signals to select said memory cell block; a sense amplifier for reading out data stored in a selected one of said memory cells in said memory cell array; first and second voltage terminals for receiving first and second voltages, respectively; a first resistor connected between said row selection circuit and said first voltage terminal; a second resistor connected between said row selection circuit and said second voltage terminal; and first and second wirings for connecting said column selection circuit and said sense amplifier to said first and second voltage terminals without through said first and second resistors, respectively.

Claim 7

A read-only semiconducto memory device comprising: a memory cell array formed of a plurality of memory cell blocks arranged in a matrix form of rows and columns, each of said memory blocks having a series circuit of a plurality of memory cells; a plurality of column lines for connecting said memory cell blocks in the column direction; a plurality of row lines for connecting said memory cells forming said memory cell blocks in the row direction; a column selection circuit having a column decoder for receiving column address signals and a column selector driven by the output of said column decoder for selecting said column lines; a row selection circuit for receiving row address signals and selecting said row lines; a memory cell block selection circuit for receiving address signals to select said memory cell block; a sense amplifier for reading out data stored in a selected one of said memory cells in said memory cell array; first and second voltage terminals for receiving first and second voltages, respectively; a first resistor connected between said row selection circuit and said first voltage terminal; a second resistor connected between said row selection circuit and said second voltage terminal; and first and second wirings for connecting said column selection circuit and said sense amplifier to said first and second voltage terminals without through said first and second resistors, respectively.

Claim 8

The memory device according to claim 5, wherein said row selection circuit includes a plurality of NAND gates.

Claim 9

A semiconductor memory device comprising: memory cells; a memory cell array formed by arranging a plurality of said memory cells in both column and row directions; a plurality of column lines for connecting said memory cells in the column direction; a plurality of row lines for connecting said memory cells in the row direction; a column selection circuit for receiving address signals and selecting said column lines; a row selection circuit for receiving the address signals and selecting said row lines; a sense amplifier for reading out data stored in the selected memory cell in said memory cell array; and an output circuit; first and second voltage terminals for receiving first and second voltages, respectively; a first resistor having a first end connected to said first voltage terminal and a second end connected to said sense amplifier circuit; a second resistor having a first end connected to said second voltage terminal and a second end connected to said sense amplifier circuit; a first wiring for connecting said output circuit to said first voltage terminal; and a second wiring for connecting said output circuit to said first voltage terminal.

Claim 10

A semiconductor memory device comprising: memory cells; a memory cell array formed by arranging a plurality of said memory cells in both column and row directions; a plurality of column lines for connecting said memory cells in the column direction; a plurality of row lines for connecting said memory cells in the row direction; a column selection circuit for receiving address signals and selecting said column lines; a row selection circuit for receiving the address signals and selecting said row lines; a sense amplifier for reading out data stored in the selected memory cell in said memory cell array; and an output circuit; first and second voltage terminals for receiving first and second voltages, respectively; a first resistor having a first end connected to said first voltage terminal and a second end connected to said sense amplifier circuit; a second resistor having a first end connected to said second voltage terminal and a second end connected to said sense amplifier circuit; a first wiring for connecting said output circuit to said first voltage terminal; and a second wiring for connecting said output circuit to said first voltage terminal.

Claim 11

The memory device according to claim 7, further comprising a first capacitor connected to the second end of said first resistor and a second capacitor connected to the second end of said second resistor.