EP0354708A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
General three dimensional packaging
Assignee: Texas Instruments Inc
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Filing: 1989-08-01
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Granted: —
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Expires: 2009-08-01
Abstract
Abstract A three dimensional package having at least one semiconductor chip 40 having input/output conductive pads 42 along its periphery includes a dielectric carrier 44 over at least a portion of the chip and a plurality of conductors 46 mounted on the carrier. The plurality of conductors 46 are mounted within the periphery of the chip with one end 48 connected to the conductive pads 42 and with the other end 53 of the plurality of conductors exiting from the same side 50 of the chip 40. The plurality of conductors 53 exiting from the same side 50 are electrically coupled to an interconnect substrate.
Inventors
- 👤 Randall E. Johnson
- 👤 James M. Drumm
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 12:24
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/611; H10W90/00; H10W90/401; H10W72/00; H10W72/01; H10W72/60; H10W72/834; H10W90/20; H10W90/284; H10W90/291; H10W90/701; H10W90/721; H10W90/724; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
74 words
A three dimensional package comprising: a first semiconductor chip having pads on its periphery, a first dielectric carrier over at least a portion of said first chip, and a first plurality of conductors positioned on said first carrier and within the periphery of said first chip, one end of said first plurality of conductors connected to the pads while the other end of the conductors exit from the same side of said first chip.
Claim 2
Dependent Claim
74 words
A three dimensional package comprising: a first semiconductor chip having pads on its periphery, a first dielectric carrier over at least a portion of said first chip, and a first plurality of conductors positioned on said first carrier and within the periphery of said first chip, one end of said first plurality of conductors connected to the pads while the other end of the conductors exit from the same side of said first chip.
Claim 3
Dependent Claim
25 words
A three dimensional package according to claim 1 wherein said first plurality of conductors are positioned between said first chip and said first dielectric carrier.
Claim 4
Dependent Claim
22 words
A package according to claim 1 wherein the first dielectric carrier is between the first plurality of conductors and said first chip.
Claim 5
Dependent Claim
22 words
A package according to claim 3 further including a first dielectric spacer between said first chip and said first plurality of conductors.
Claim 6
Dependent Claim
82 words
A package according to claim 1 further including a second semiconductor chip having second pads on its periphery, a second dielectric carrier over at least a portion of said second chip, and a second plurality of conductors positioned on said second carrier and within the periphery of said second chip, one end of said second plurality of conductors connected to said second pads while the other end of said second conductors exit from the same side as those from said first chip.
Claim 7
Dependent Claim
22 words
A package according to claim 5 wherein said second dielectric carrier is between said second plurality of conductors and said second chip.
Claim 8
Dependent Claim
41 words
A package according to claim 5 further including an interconnect substrate having a plurality of conductive means thereon which electrically interconnect to said first and second plurality of conductors which exit from the same side of said first and second chips.
Claim 9
Dependent Claim
18 words
A package according to claim 7 wherein said first and second chips and said interconnect substrate are orthogonal.
Claim 10
Dependent Claim
171 words
A three dimensional packaging system comprising: an interconnect substrate, a plurality of 3D packages mounted orthogonally on said interconnect substrate, each of said 3D packages comprising: a first semiconductor chip having first pads on its periphery, a first dielectric carrier over at least a portion of said first chip, and a first plurality of conductors positioned on said first carrier and within the periphery of said first chip, one end of said first plurality of conductors connected to said first pads while the other end of the conductors exit from the same side of said first chip, a second semiconductor chip having second pads on its periphery, a second dielectric carrier over at least a portion of said second chip, and a second plurality of conductors positioned on said second carrier and within the periphery of said second chip, one end of said second plurality of conductors connected to said second pads while the other end of said second conductors exit from the same side as those from said first chip.
Claim 11
Dependent Claim
171 words
A three dimensional packaging system comprising: an interconnect substrate, a plurality of 3D packages mounted orthogonally on said interconnect substrate, each of said 3D packages comprising: a first semiconductor chip having first pads on its periphery, a first dielectric carrier over at least a portion of said first chip, and a first plurality of conductors positioned on said first carrier and within the periphery of said first chip, one end of said first plurality of conductors connected to said first pads while the other end of the conductors exit from the same side of said first chip, a second semiconductor chip having second pads on its periphery, a second dielectric carrier over at least a portion of said second chip, and a second plurality of conductors positioned on said second carrier and within the periphery of said second chip, one end of said second plurality of conductors connected to said second pads while the other end of said second conductors exit from the same side as those from said first chip.
Claim 12
Independent Claim
87 words
A method of fabricating a three dimensional package including a semiconductor chip having conductive I/O pads along its periphery comprising the steps of: forming a dielectric carrier sized less than the periphery of said chip, placing a plurality of conductors on said carrier, one end of said plurality of conductors positioned over said I/O pads while the other ends of said plurality exit from the same side of said chip, and electrically connecting said conductors exiting from the same side of said chip to an interconnect substrate.
Claim 13
Independent Claim
87 words
A method of fabricating a three dimensional package including a semiconductor chip having conductive I/O pads along its periphery comprising the steps of: forming a dielectric carrier sized less than the periphery of said chip, placing a plurality of conductors on said carrier, one end of said plurality of conductors positioned over said I/O pads while the other ends of said plurality exit from the same side of said chip, and electrically connecting said conductors exiting from the same side of said chip to an interconnect substrate.
Claim 14
Dependent Claim
82 words
A three dimensional package comprising: a first semiconductor chip having pads on its periphery, a first dielectric carrier over at least a portion of said first chip, and a first plurality of conductors positioned on the carrier between said first chip and said first dielectric carrier and within the periphery of said first chip, one end of said first plurality of conductors connected to the pads while the other end of the conductors exit from the same side of said first chip.
Claim 15
Dependent Claim
82 words
A three dimensional package comprising: a first semiconductor chip having pads on its periphery, a first dielectric carrier over at least a portion of said first chip, and a first plurality of conductors positioned on the carrier between said first chip and said first dielectric carrier and within the periphery of said first chip, one end of said first plurality of conductors connected to the pads while the other end of the conductors exit from the same side of said first chip.
Claim 16
Dependent Claim
23 words
A package according to claim 11 further including a first dielectric spacer positioned between said first chip and said first plurality of conductors.
Claim 17
Dependent Claim
89 words
A package according to claim 11 further including a second semiconductor chip having second pads on its periphery, a second dielectric carrier over at least a portion of said second chip, and a second plurality of conductors mounted on the carrier between said second chip and said second dielectric carrier and within the periphery of said second chip, one end of said second plurality of conductors connected to said second pads while the other end of the conductors exit from the same side as those from said first chip.
Claim 18
Dependent Claim
41 words
A package according to claim 13 further including an interconnect substrate having a plurality of conductive means thereon which electrically interconnect to said first and second plurality of conductors which exit from the same side of said first and second chips.
Claim 19
Independent Claim
99 words
A method of fabricating a three dimensional package including a semiconductor chip having conductive I/O pads along its periphery comprising the steps of: forming a dielectric carrier sized less than the periphery of said chip, affixing a plurality of conductors on said carrier, positioning said carrier and plurality of conductors over said chip such that said conductors extend parallel to said chip with one end overlaying said conductive pads while the other ends of said plurality exit from the same side of said chip, and electrically connecting said I/O pads to said one end of said plurality of conductors.
Claim 20
Independent Claim
99 words
A method of fabricating a three dimensional package including a semiconductor chip having conductive I/O pads along its periphery comprising the steps of: forming a dielectric carrier sized less than the periphery of said chip, affixing a plurality of conductors on said carrier, positioning said carrier and plurality of conductors over said chip such that said conductors extend parallel to said chip with one end overlaying said conductive pads while the other ends of said plurality exit from the same side of said chip, and electrically connecting said I/O pads to said one end of said plurality of conductors.
References Cited (Backward Citations)
No citation records indexed.
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