EP0361972A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Non-volatile semiconductor memory device with nand type memory cell arrays
Assignee: Toshiba Corp
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Filing: 1989-09-29
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Granted: —
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Expires: 2009-09-29
Abstract
Abstract An electrically erasable programmable read-only memory is disclosed which has programmable memory cells (M) connected to parallel bit lines (BL) provided above a semiconductor substrate. The memory cells include NAND cell blocks each of which has a series array of memory cell transistors (M1 to M8). Parallel word lines are connected to the control gates of the memory cell transistors, respectively. In a data write mode, a selection transistor (Qs1) in a certain NAND cell block including a selected memory cell is rendered conductive to connect the certain cell block to a corresponding bit line associated therewith. Under such a condition, electrons are tunnel-injected into a floating gate of the selected memory cell transistor, and the threshold value of the certain transistor is increased to be a positive value. A logical data is thus written in the selected memory cell transistor. The data in the selected cell transistor is erased by discharging carriers accumulated in the floating gate thereof to its drain or the substrate, so that the threshold value of the certain transistor is decreased to be a negative value.
Inventors
- 👤 Ryouhei Intellectual Property Division Kirisawa
- 👤 Riichiro Intellectual Property Division Shirota
- 👤 Ryozo Intellectual Property Division Nakayama
- 👤 Seichi Intellectual Property Division Aritome
- 👤 Masaki Intellectual Property Division Momodomi
- 👤 Yasuo Intellectual Property Division Itoh
- 👤 Fujio Intellectual Property Division Masuoka
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 20:13
CPC Classifications
G; G11; G11C; G11C17/00; G11C16/00; G11C16/02; G11C16/04; G11C16/0483; G11C16/06; G11C16/10
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
186 words
A non-volatile semiconductor memory device comprising a semiconductive substrate (22), parallel bit lines (BL) provided above said substrate, and memory cells (M) connected to said bit lines, said memory cells comprising NAND cell blocks (B) each of which has a series array of memory cell transistors (M11, M12, M13, M14, M15, M16, M17, M18) connected at a first node thereof to a corresponding bit line (BL1) associated therewith and connected at a second node thereof to said substrate (22), each of said memory cell transistors having a carrier storage layer (28) and a control gate electrode (32), characterized in that said device further comprises: means (WL, 10, 12) for writing a logical data into a certain memory cell transistor which is selected from said memory cell transistors by injecting carriers by tunneling into the carrier storage layer (28) of said certain memory cell transistor thereby to increase a threshold value thereof, and for erasing the data stored in said certain memory cell transistor by removing the carriers accumulated in said carrier storage layer (28) thereby to decrease the threshold value of said certain memory cell transistor.
Claim 2
Dependent Claim
186 words
A non-volatile semiconductor memory device comprising a semiconductive substrate (22), parallel bit lines (BL) provided above said substrate, and memory cells (M) connected to said bit lines, said memory cells comprising NAND cell blocks (B) each of which has a series array of memory cell transistors (M11, M12, M13, M14, M15, M16, M17, M18) connected at a first node thereof to a corresponding bit line (BL1) associated therewith and connected at a second node thereof to said substrate (22), each of said memory cell transistors having a carrier storage layer (28) and a control gate electrode (32), characterized in that said device further comprises: means (WL, 10, 12) for writing a logical data into a certain memory cell transistor which is selected from said memory cell transistors by injecting carriers by tunneling into the carrier storage layer (28) of said certain memory cell transistor thereby to increase a threshold value thereof, and for erasing the data stored in said certain memory cell transistor by removing the carriers accumulated in said carrier storage layer (28) thereby to decrease the threshold value of said certain memory cell transistor.
Claim 3
Dependent Claim
116 words
The device according to claim 1, characterized in that said means stores in a selected memory cell transistor (M13) of a certain NAND cell block (BL1) a data to be written supplied from a corresponding bit line (BL1) associated with said certain NAND cell block (B1), by applying an "H" level voltage to the control gate (CG3) of said selected transistor (M13), applying the control gates (CG1, CG2, CG4 to CG8) of non-selected memory cell transistors (M11, M12, M14 to M18) of said certain cell block (B1) with an intermediate voltage (Vm) which is lower than the "H" level voltage and yet higher than an "L" level voltage in a data write mode of said device.
Claim 4
Dependent Claim
123 words
The device according to claim 2, characterized in that said means erases the content of said selected memory cell transistor (M13), by applying the "L" level voltage to the control gate (CG3) of said selected transistor, applying the "H" level voltage to the control gates (CG1, CG2) of first non-selected memory cell transistors (M11, M12) of said certain NAND cell block (B1) which are positioned between said selected transistor (M13) and the corresponding bit line (BL1) associated with said cell block, and applying the "L" level voltage to the control gates (CG4 to CG8) of second non-selected memory cell transistors consisting of the remaining memory cell transistors (M14 to M18) of said certain cell block in a data erase mode of said device.
Claim 5
Dependent Claim
31 words
The device according to claim 3, characterized in that said means sequentially designates one of the memory cell transistors included in said certain cell block (B1) in the data write mode.
Claim 6
Dependent Claim
31 words
The device according to claim 3, characterized in that said means sequentially designates one of the memory cell transistors included in said certain cell block (B1) in the data erase mode.
Claim 7
Dependent Claim
92 words
The device according to claim 4, characterized in that said means first selects from said certain cell block (B1) a specific memory cell transistor (M18) which is positioned fartherest from said first node of said certain cell block (B1) along said series array of memory cell transistors (M11 to M18) of said certain cell block (B1) in the data write mode, and select lastly another specific memory cell transistor (M11) from said certain cell block, said another specific memory cell transistor being positioned nearest to said first node along said series array.
Claim 8
Dependent Claim
92 words
The device according to claim 5, characterized in that said means first selects from said certain cell block (B1) a specific memory cell transistor (M11) which is positioned nearest to said first node of said certain cell block along said series array of memory cell transistors (M11 to M18) of said certain cell block (B1) in the data erase mode, and select lastly another specific memory cell transistor (M18) from said certain cell block, said another specific memory cell transistor (M18) being positioned fartherest from said first node along said series array.
Claim 9
Dependent Claim
92 words
The device according to claim 5, characterized in that said means first selects from said certain cell block (B1) a specific memory cell transistor (M18) which is positioned fartherest from said first node of said certain cell block along said series array of memory cell transistors (M11 to M18) of said certain cell block (B1) in the data erase mode, and select lastly another specific memory cell transistor (M11) from said certain cell block, said another specific memory cell transistor (M11) being positioned nearest to said first node along said series array.
Claim 10
Dependent Claim
25 words
The device according to claim 8, characterized in that said means uses a power supply voltage (Vcc) of said device as said intermediate voltage (Vm).
Claim 11
Dependent Claim
352 words
An electrically erasable programmable read-only memory device comprising a semiconductive substrate (22), parallel bit lines (BL) provided above said substrate, parallel word lines (WL) provided on said substrate so as to define crossing points between said bit lines (BL) and said word lines (WL), double gate field effect transistors (M) provided at said crossing points to serve as memory cells of said device, said transistors including a cell array (B1) which has a series-circuit of cell transistors (M11 to M18) for constituting a NAND cell structure, each of said cell transistors having an electrically floating gate (28) and a control gate (32) which is connected to a corresponding word line (WL1), a field effect transistor (Qs12) which is provided in said cell array has a gate layer (36), and serves as a switching transistor which selectively connects said cell array (B1) to a substrate voltage (Vs), and a gate control line (SG2) connected to said gate layer (36) of said switching transistor (Qs12), characterized in that erase means (10, 12, CG1 to CG8) is connected to said word lines and said gate control line, for, when a desired cell is sequentially selected from among the memory cells (M11 to M18) of said cell array (B1), (i) applying said gate gate control line (SG2) with an "L" level voltage which renders said switching transistor (Qs12) nonconductive thereby to disconnect said cell array (B1) from said substrate voltage (Vs), (ii) for applying the "L" level voltage to a selected word line (WL3) which is connected with said desired cell (M13), (iii) for applying an "H" level voltage to word lines (WL1, WL2) connected to first non-selected memory cells (M11, M12) of said cell array which are positioned between said desired cell (M13) and corresponding bit line (BL1) associated with said cell array (B1), and (iv) for applying the "L" level voltage to word lines (WL4 to WL8) which are connected to second non-selected memory cells (M14 to M18) of said cell array which are positioned between said desired cell (M13) and said switching transistor (Qs12), whereby said desired cell is subjected to data erasing.
Claim 12
Dependent Claim
352 words
An electrically erasable programmable read-only memory device comprising a semiconductive substrate (22), parallel bit lines (BL) provided above said substrate, parallel word lines (WL) provided on said substrate so as to define crossing points between said bit lines (BL) and said word lines (WL), double gate field effect transistors (M) provided at said crossing points to serve as memory cells of said device, said transistors including a cell array (B1) which has a series-circuit of cell transistors (M11 to M18) for constituting a NAND cell structure, each of said cell transistors having an electrically floating gate (28) and a control gate (32) which is connected to a corresponding word line (WL1), a field effect transistor (Qs12) which is provided in said cell array has a gate layer (36), and serves as a switching transistor which selectively connects said cell array (B1) to a substrate voltage (Vs), and a gate control line (SG2) connected to said gate layer (36) of said switching transistor (Qs12), characterized in that erase means (10, 12, CG1 to CG8) is connected to said word lines and said gate control line, for, when a desired cell is sequentially selected from among the memory cells (M11 to M18) of said cell array (B1), (i) applying said gate gate control line (SG2) with an "L" level voltage which renders said switching transistor (Qs12) nonconductive thereby to disconnect said cell array (B1) from said substrate voltage (Vs), (ii) for applying the "L" level voltage to a selected word line (WL3) which is connected with said desired cell (M13), (iii) for applying an "H" level voltage to word lines (WL1, WL2) connected to first non-selected memory cells (M11, M12) of said cell array which are positioned between said desired cell (M13) and corresponding bit line (BL1) associated with said cell array (B1), and (iv) for applying the "L" level voltage to word lines (WL4 to WL8) which are connected to second non-selected memory cells (M14 to M18) of said cell array which are positioned between said desired cell (M13) and said switching transistor (Qs12), whereby said desired cell is subjected to data erasing.
Claim 13
Dependent Claim
87 words
The device according to claim 10, characterized in that said erase means executes a sequential data erasing operation in such a manner that a specific memory cell (M11) which is positioned in adjacent to a connection node between said cell array (B1) and said bit line (B1) associated therewith is first selected from said cell array (B1) and that another specific memory cell (M18) which is positioned in adjacent to said switching transistor (Qs12) included in said cell array (B1) is selected lastly from said cell array.
Claim 14
Dependent Claim
87 words
The device according to claim 10, characterized in that said erase means executes a sequential data erasing operation in such a manner that a specific memory cell (M18) which is positioned in adjacent to said switching transistor (Qs12) included in said cell array is first selected from said cell array (B1) and that another specific memory cell (M11) which is positioned in adjacent to a connection node between said cell array (B1) and said bit line (BL1) associated therewith is selected lastly from said cell array (B1).
Claim 15
Dependent Claim
161 words
The device according to claim 10, characterized by further comprising: write means (10, 12, CG1 to CG8) connected to said word lines and said gate control line, for, when a selected cell is sequentially designated from among the memory cells of said cell array, (i) applying said gate control line (SG2) with the "L" level voltage which renders said switching transistor (QS12) nonconductive thereby to disconnect said cell array (B1) from said substrate voltage (Vs), (ii) for applying the "H" level voltage to a selected word line (WL4) which is connected with said desired cell (M14), (iii) for applying an intermediate voltage (Vm) of a voltage potential between the "H" level voltage and the "L" level voltage to word lines (WL1 to WL3, WL5 to WL8) connected to non-selected memory cells (M11 to M13, M15 to M18) of said cell array (B1), whereby a logical data which is supplied from said bit line (BL1) is stored in the desired cell (M14).
Claim 16
Dependent Claim
85 words
The device according to claim 13, characterized in that said write means executes a sequential data writing operation in such a manner that a specific memory cell (M18) which is positioned in adjacent to said switching transistor (Qs12) included in said cell array (B1) is first selected from said cell array and that another specific memory cell (M11) which is positioned nearest to a connection node between said cell array (B1) and said bit line (BL1) associated therewith is selected lastly from said cell array.
Claim 17
Dependent Claim
31 words
The device according to claim 14, characterized in that said write means uses as said intermediate voltage (Vm) a power supply voltage (Vcc) which is externally supplied to said memory device.
Claim 18
Dependent Claim
24 words
The device according to claim 15, characterized in that said power supply voltage (Vcc) is a d.c. voltage which is lower than 10 volts.
Claim 19
Dependent Claim
183 words
A data accessing method for a non-volatile semiconductor memory device comprising, parallel bit lines (BL) provided above a semiconductive substrate, memory cells (M) connected to said bit lines, said memory cells comprising NAND cell blocks (B) each of which has a series array of memory cell transistors (M11, M12, M13, M14, M15, M16, M17, M18) connected at a first node thereof to a corresponding bit line (BL1) associated therewith and connected at a second node thereof to said substrate (22), each of said memory cell transistors having a carrier storage layer (28) and a control gate electrode (32), characterized in that said method comprises the steps of: writing a logical data into a certain memory cell transistor which is selected from said memory cell transistors by injecting carriers by tunneling into the carrier storage layer (28) of said certain memory cell transistor thereby to increase a threshold value thereof; and erasing the data stored in said certain memory cell transistor by removing the carriers accumulated in said carrier storage layer (28) thereby to decrease the threshold value of said certain memory cell transistor.
Claim 20
Dependent Claim
183 words
A data accessing method for a non-volatile semiconductor memory device comprising, parallel bit lines (BL) provided above a semiconductive substrate, memory cells (M) connected to said bit lines, said memory cells comprising NAND cell blocks (B) each of which has a series array of memory cell transistors (M11, M12, M13, M14, M15, M16, M17, M18) connected at a first node thereof to a corresponding bit line (BL1) associated therewith and connected at a second node thereof to said substrate (22), each of said memory cell transistors having a carrier storage layer (28) and a control gate electrode (32), characterized in that said method comprises the steps of: writing a logical data into a certain memory cell transistor which is selected from said memory cell transistors by injecting carriers by tunneling into the carrier storage layer (28) of said certain memory cell transistor thereby to increase a threshold value thereof; and erasing the data stored in said certain memory cell transistor by removing the carriers accumulated in said carrier storage layer (28) thereby to decrease the threshold value of said certain memory cell transistor.
Claim 21
Dependent Claim
124 words
The method according to claim 17, characterized in that, when a selected memory cell transistor (M13) of a certain NAND cell block (BL1) is designated, a data to be written supplied from a corresponding bit line (BL1) associated with said certain NAND cell block (B1) is stored in said selected memory cell transistor (M13) by applying an "H" level voltage to the control gate (CG3) of said selected transistor (M13), applying the control gates (CG1, CG2, CG4 to CG8) of non-selected memory cell transistors (M11, M12, M14 to M18) of said certain cell block (B1) with an intermediate voltage (Vm) which is lower than the "H" level voltage and yet higher than an "L" level voltage in a data write mode of said device.
Claim 22
Dependent Claim
122 words
The method according to claim 18, characterized in that the content of said selected memory cell transistor (M13) is erased by applying the "L" level voltage to the control gate (CG3) of said selected transistor, applying the "H" level voltage to the control gates (CG1, CG2) of first non-selected memory cell transistors (M11, M12) of said certain NAND cell block (B1) which are positioned between said selected transistor (M13) and the corresponding bit line (BL1) associated with said cell block, and applying the "L" level voltage to the control gates (CG4 to CG8) of second non-selected memory cell transistors consisting of the remaining memory cell transistors (M14 to M18) of said certain cell block in a data erase mode of said device.
Claim 23
Dependent Claim
28 words
The method according to claim 19, characterized in that the memory cell transistors included in said certain cell block (B1) are sequentially designated in the data write mode.
Claim 24
Dependent Claim
28 words
The method according to claim 19, characterized in that the memory cell transistors included in said certain cell block (B1) are sequentially designated in the data erase mode.
Claim 25
Dependent Claim
95 words
The method according to claim 20, characterized in that a specific memory cell transistor (M18) which is positioned fartherest from said first node of said certain cell block (B1) along said series array of memory cell transistors (M11 to M18) of said certain cell block (B1) is first selected from said certain cell block (B1) in the data write mode, and in that another specific memory cell transistor (M11) is lastly selected from said certain cell block, said another specific memory cell transistor (M11) being positioned nearest to said first node along said series array.
Claim 26
Dependent Claim
94 words
The method according to claim 21, characterized in that a specific memory cell transistor (M11) which is positioned nearest to said first node of said certain cell block along said series array of memory cell transistors (M11 to M18) of said certain cell block (B1) is first selected from said certain cell block (B1) in the data erase mode, and in that another specific memory cell transistor (M18) is lastly selected from said certain cell block, said another specific memory cell transistor (M18) being positioned fartherest from said first node along said series array.
Claim 27
Dependent Claim
94 words
The method according to claim 21, characterized in that a specific memory cell transistor (M18) which is positioned fartherest from said first node of said certain cell block along said series array of memory cell transistors (M11 to M18) of said certain cell block (B1) is first selected from said certain cell block (B1) in the data erase mode, and in that another specific memory cell transistor (M11) is lastly selected from said certain cell block, said another specific memory cell transistor (M11) being positioned nearest to said first node along said series array.
References Cited (Backward Citations)
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