EP0362050A2
Expired / Lapsed
EP
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Memory card
Assignee: Fujitsu VLSI Ltd
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Filing: 1989-09-26
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Granted: —
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Expires: 2009-09-26
Abstract
Abstract A memory card is used on a card write and/or read apparatus which has a data bus with an arbitrary bit width and writes and/or reads a datum to and/or from the memory card. The memory card comprises a data input/output terminal (5, 21, 62a, 62b), a memory part (1, 12, 13, M0-M7) having a data bus with a bit width of at least n bits for coupling to the data bus of the card write and/or read apparatus via the data input/output terminal, an address input terminal (2, 16, 70) for receiving an address signal, a first input terminal (7, 19, 66) for receiving a first chip select signal which selects a first byte, a second input terminal (8, 20, 65) for receiving a second chip select signal which selects a second byte, and a decoder circuit (9, 15, 61) for determining a bit width of the data bus of the memory part to be used for data communication between the card write and/or read apparatus to one of n bits and n/N bits based on the first and second chip select signals and one or a plurality of arbitrary bits of the address signal by supplying control signals to the memory part, where n, N and n/N are positive integers.
Inventors
- 👤 Masaru Masuyama
- 👤 Yoshihiro Takemae
- 👤 Tetsuhiko Endoh
- 👤 Hirosuke Komyoji
- 👤 Ryuji Tanaka
- 👤 Katsuhiko Itakura
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-25 07:06
CPC Classifications
G; G06; G06K; G06K19/00; G06K19/06; G06K19/067; G06K19/07; G06K7/00; G06K7/0008
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
219 words
A memory card for use on a card write and/or read apparatus which has a data bus with an arbitrary bit width and writes and/or reads a datum to and/or from said memory card, said memory card comprising data input/output terminal means (5, 21, 62a, 62b); memory means (1, 12, 13, M0-M7) having a data bus with a bit width of at least n bits for coupling to the data bus of the card write and/or read apparatus via said data input/output terminal means; and address input terminal means (2, 16, 70) for receiving an address signal, characterized in that there are further provided: first input terminal means (7, 19, 66) for receiving a first chip select signal which selects a first byte; second input terminal means (8, 20, 65) for receiving a second chip select signal which selects a second byte; and decoder means (9, 15, 61) for determining a bit width of the data bus of said memory means to be used for data communication between the card write and/or read apparatus to one of n bits and n/N bits based on the first and second chip select signals and one or a plurality of arbitrary bits of the address signal by supplying control signals to said memory means, where n, N and n/N are positive integers.
Claim 2
Dependent Claim
219 words
A memory card for use on a card write and/or read apparatus which has a data bus with an arbitrary bit width and writes and/or reads a datum to and/or from said memory card, said memory card comprising data input/output terminal means (5, 21, 62a, 62b); memory means (1, 12, 13, M0-M7) having a data bus with a bit width of at least n bits for coupling to the data bus of the card write and/or read apparatus via said data input/output terminal means; and address input terminal means (2, 16, 70) for receiving an address signal, characterized in that there are further provided: first input terminal means (7, 19, 66) for receiving a first chip select signal which selects a first byte; second input terminal means (8, 20, 65) for receiving a second chip select signal which selects a second byte; and decoder means (9, 15, 61) for determining a bit width of the data bus of said memory means to be used for data communication between the card write and/or read apparatus to one of n bits and n/N bits based on the first and second chip select signals and one or a plurality of arbitrary bits of the address signal by supplying control signals to said memory means, where n, N and n/N are positive integers.
Claim 3
Dependent Claim
32 words
The memory card as claimed in claim 1, characterized in that said address signal and said first and second chip select signals are respectively received from the card write and/or read apparatus.
Claim 4
Dependent Claim
73 words
The memory card as claimed in claim 1 or 2, characterized in that said memory means (1, 12, 13, M0-M7) comprises a first n/2-bit output memory (12) and a second n/2-bit output memory (13) which respectively have an output of n/2 bits, said first and second n/2-bit output memories being enabled by the control signals received from said decoder means (9, 15, 61) and determining the bit width of the data bus used.
Claim 5
Dependent Claim
54 words
The memory card as claimed in claim 3, characterized in that n = 16 and N = 2, said first n/2-bit output memory (12) being used for writing and reading the first byte of the datum, said second n/2-bit output memory (13) being used for writing and reading the second byte of the datum.
Claim 6
Dependent Claim
131 words
The memory card as claimed in any of claims 1 to 4, characterized in that there are further provided third input terminal means (17, 63) for receiving a write enable signal and input buffer means (11) for receiving the first and second chip select signals and the write enable signals from said first, second and third input terminal means (7, 19, 66; 8, 20, 65; 17, 63) and the address signal from said address input terminal means (2, 16, 70), said input buffer means supplying the write enable signal and bits of the address signal excluding the one or plurality of arbitrary bits to said memory means (1, 12, 13, M0-M7), write and read operations of said memory means being enabled depending on a logic value of said write enable signal.
Claim 7
Dependent Claim
89 words
The memory card as claimed in claim 5, characterized in that there are further provided fourth input terminal means (18, 64) for receiving an output enable signal and input/output buffer means (14) coupled to said memory means (1, 12, 13, M0-M7) for receiving a datum to be written into said memory means via said data input/output terminal means (5, 21, 62a, 62b) and for outputting a datum read out from said memory means to said data input/output terminal means depending on a logic value of the output enable signal.
Claim 8
Dependent Claim
30 words
The memory card as claimed in claim 6, characterized in that said write enable signal and said output enable signal are respectively received from the card write and/or read apparatus.
Claim 9
Dependent Claim
22 words
The memory card as claimed in any of claims 1 to 7, characterized in that n = 16 and N = 2.
Claim 10
Dependent Claim
53 words
The memory card as claimed in claim 1 or 2, characterized in that said memory means (1, 12, 13, M0-M7) comprises a plurality of n/2-bit output memories (M0-M7) which respectively have an output of n/2 bits, said n/2-bit output memories being respectively enabled by the control signals received from said decoder means (61).
Claim 11
Dependent Claim
49 words
The memory card as claimed in any of claims 1 to 9, characterized in that said first and second chip select signals have logic values which are selected depending on the bit width of the data bus of the card write and/or read apparatus which uses said memory card.
References Cited (Backward Citations)
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