EP0363222A2
Expired / Lapsed
EP
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Method and apparatus for concurrent dispatch of instructions to multiple functional units
Assignee: HP Inc
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Filing: 1989-10-06
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Granted: —
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Expires: 2009-10-06
Abstract
Abstract Apparatus and method for concurrent dispatch of instruction words which selectively comprise instruction components which are separately and substantially simultaneously received by distinct floating points and integer functional units. The instruction words are powers of 2 in length, (measured in terms of the smallest machine addressable unit) typically a 4 byte longword and an 8 byte quadword aligned to the natural boundaries also corresponding to powers of 2. To provide maximum operating efficiency, every functional (or processing) unit execute to component of the instruction word during the same execution cycle. The type and length of the instruction are indicated by one of the bit fields of the instruction word, which permits the apparatus to properly detect, store and transfer the instruction word to the appropriate functional unit. The invention provides the encoding efficiency of variable length instructions combined with enhanced processing speed of simultaneous operation of all available functional units while retaining the execution efficiency of systems with a single instruction length.
Inventors
- 👤 John S. Yates, Jr.
- 👤 John Manton
- 👤 Richard G. Bahr
- 👤 Stephen J. Ciavaglia
- 👤 Michael Kahaiyan
- 👤 Barry J. Flahive
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-25 03:39
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3885; G06F9/3889; G06F9/30145; G06F9/30149; G06F9/32; G06F9/321; G06F9/3802; G06F9/3814; G06F9/3816; G06F9/3836; G06F9/3853
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
127 words
Apparatus for multiple concurrent instructions dispatch, comprising: means for providing an instruction word having a plurality of instruction types including two instruction of a first type an instruction of a first type and second type instruction; an instruction cache receiving said instruction word and selectively comprising said instruction word and having two instruction areas for storing two of said first type and said second type instruction; a first processor for receiving said first type instructions from said instruction cache for the processing of data applied to said first processor; and a second processor for receiving said second type of instruction from said instruction cache (simultaneously with the receipt of said first type instruction by said first processor) for the processing of data applied to said second processor.
Claim 2
Dependent Claim
127 words
Apparatus for multiple concurrent instructions dispatch, comprising: means for providing an instruction word having a plurality of instruction types including two instruction of a first type an instruction of a first type and second type instruction; an instruction cache receiving said instruction word and selectively comprising said instruction word and having two instruction areas for storing two of said first type and said second type instruction; a first processor for receiving said first type instructions from said instruction cache for the processing of data applied to said first processor; and a second processor for receiving said second type of instruction from said instruction cache (simultaneously with the receipt of said first type instruction by said first processor) for the processing of data applied to said second processor.
Claim 3
Dependent Claim
54 words
The apparatus of claim 1 further including: pre-fetch register means for transferring said first type instruction from one of said instruction area to a receiving processor comprising the processor associated with the other of the instruction area when said instruction cache has two of said first instruction types stored in said two instruction areas.
Claim 4
Dependent Claim
40 words
The apparatus of claim 2, wherein said means for providing includes: means for incrementing the address signal of said cache wherein: said means for incrementing is inhibited upon the transfer of instructions from said pre-fetch register to the receiving processor.
Claim 5
Dependent Claim
39 words
The apparatus of claim 1, further including: means for providing said first type of instruction and at least a portion of said second type instructions to one of said first and second from both of said two instruction area.
Claim 6
Dependent Claim
29 words
The apparatus of claim 1, further including: means for selectively providing an instruction to said one of said first and second processors from one of said two instruction areas.
Claim 7
Dependent Claim
42 words
The apparatus of claim 5, wherein said first processor provides condition code and instruction code decode signals in response to the received first type instruction, and said means for selectively providing is responsive to said condition code and instruction code decode signals.
Claim 8
Dependent Claim
21 words
The apparatus of claim 6, wherein said first processor comprises a pipeline processor including means for providing a program counter signal.
Claim 9
Dependent Claim
40 words
The apparatus of claim 7 wherein said means for providing a program counter signal selectively increments said program counter by one of zero, the incremental value of the next instruction type and the incremental value of the next instruction word.
Claim 10
Dependent Claim
69 words
The apparatus of claim 8 wherein said instruction word includes 64 instruction bits comprising 8 bytes of 8 bits per byte; said first and second instruction type comprises 4 bytes of 8 bits per byte; said means for selectively providing includes means for addressing each instruction word byte; said incremented value of the next instruction type is 4; and said incremented value of the next instruction word is 8.
Claim 11
Dependent Claim
39 words
The apparatus of claim 8, further including pre-fetch register means for receiving a first type instruction from said instruction cache, and for providing said first type instruction to said first processor when said instruction counter is incremented by zero.
Claim 12
Dependent Claim
55 words
The apparatus of claim 10, wherein said first processor further includes branch means responsive to said instruction code decode and said condition code signals for providing a branch signal to said means for providing a program counter signal, wherein said branch signal is an integer multiple of said incremental value of the next instruction type.
References Cited (Backward Citations)
No citation records indexed.
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