Bus for a data processing system

Claim 2

An Advanced Processor Bus system for communicating data words among at least one processor connecting to the AP Bus by at least one bus interface means such as a Bus Expander Unit; and at least one memory array connecting to the AP Bus by at least memory control mans, such as a Memory Control Unit, wherein said bus interface means connected to respective processors issue data requests request the transmission of data upon the AP Bus for reception into a register of each said bus interface means making such request; and said bus interface means and said memory control means issue data replies communicating over the AP Bus in response to the data requests by transmission of the requested data, memory control means issue data replies communicating over the AP Bus in response to the data requests by transmission of the requested data, said AP Bus system comprising: message generator means for generating messages in the form of packets of information for transmission on said Bus system, said messages being divided into message types including control message packets, request message packets, and reply message packets, each packet comprising at least one bus transmission slot issued by said message generator means sequentially and contiguously, each bus transmission slot in a packet being capable of including operation specification code, address, data, control, and parity-check bits; a pipeline queue; message controller means connected to said message generator means and to said pipeline queue for controlling said request message packets, said control message packets and said reply message packets such that a predetermined number of said request message packets and control message packets requiring reply message packets may be entered into said pipeline queue at any one time; monitor means connected to said message controller means and to said Bus system for monitoring said request message packets and control message packets, and said reply message packets communicated on said bus by said message generator, preventing request message packet replies in excess of said predetermined number from being communicated on said bus until a reply message packet is communicated on said bus to thereby make available a slot in the pipeline queue; control signal connections as a part of said AP Bus operative in parallel with the data portion thereof for providing a coded signal indicating a particular message type communicated on said bus by said message generator; and interface logic means connected to said message generator means and to said control signal lines for communicating over said AP Bus system the type of message packet generated; said message generator means including means for inserting a particular reply message packet corresponding to a particular request message packet in said pipeline queue at a position in said pipeline queue corresponding to the request message packet that is associated with said particular reply message packet.

Claim 3

An Advanced Processor Bus system for use in a data processing system using VLSI Advanced Processor components, having AP Bus interface units for processors as AP nodes and memory interface units as AP Bus nodes; said AP Bus connecting to and communicating among each of said nodes, comprising: recognizing means connected to said Advanced Processor Bus for recognizing signals on said AP Bus representative of a request to one of said nodes; means connected to said AP Bus, responsive to said recognizing means, for generating on said Bus, signals representative of a first and a second write-request packets, and a first and second read request packets, said packets comprising a number of bus transmission slots, issued sequentially and contiguously, each slot in a packet including: operation-specification bits; address bits; data bits; and control bits; said first write-request packet including an operation specification code specifying a write function to be performed and a memory location where the information bits are written to, and said second write-request packet including an operation specification code specifying a function to be performed and a memory mapped location where the information bits are to be written to; said first read request packet including an operation specification code specifying a read function to be performed and a memory location where the information bits are read from, and said second read request packet including an operation specification code specifying a function to be performed and a memory mapped location where the information bits are read from; said memory mapped locations corresponding to inter-agent communications specifying an internal destination code of an agent and the functions desired of the specified agent; receiving means connected to said AP Bus for receiving a reply message packet on said AP Bus system, said reply message packet including a number of bus transmission slots, received sequentially and contiguously, each slot in said reply packet including operation specification code, data bits and control bits; said reply message packet containing an operation specification code and if requested data; message control means connected to said generating means and said receiving means said message control means including as a part of said message control means: means for queuing data in said write request packets, means responsive to said control bits in said read packets, and write packets for detecting a beginning and an end of each packet, means for decoding each said operation specification code to indicate the operation specified, means for establishing a pipeline for said request message packets, and said reply message packets generated on said AP Bus by said message generator, monitor means connected to said message control means and to said AP Bus system, for monitoring signals on said AP Bus system representative of said request packets, and reply packets on said bus, such that a request packet is prevented from entering said pipeline until a reply packet is received to make available a slot in said pipline, whereby request packets increase the length of said pipeline up to a predetermined number of request packets in said pipeline, and reply packets decrease the length of said pipeline; and means connected to said recognizing means, said generating means, said message control means and said receiving means, for arbitrating said signals on said Bus system representative of requests going onto said Bus system and said signals on said Bus system representative of replies received on said Bus, to enable said message control means to insert a reply packet associated with a particular request packet in the pipeline position of said recognized request packet.

Claim 4

An Advanced Processor Bus system for use in a data processing system using VLSI Advanced Processor components, having AP Bus interface units for processors as AP nodes and memory interface units as AP Bus nodes; said AP Bus connecting to and communicating among each of said nodes, comprising: recognizing means connected to said Advanced Processor Bus for recognizing signals on said AP Bus representative of a request to one of said nodes; means connected to said AP Bus, responsive to said recognizing means, for generating on said Bus, signals representative of a first and a second write-request packets, and a first and second read request packets, said packets comprising a number of bus transmission slots, issued sequentially and contiguously, each slot in a packet including: operation-specification bits; address bits; data bits; and control bits; said first write-request packet including an operation specification code specifying a write function to be performed and a memory location where the information bits are written to, and said second write-request packet including an operation specification code specifying a function to be performed and a memory mapped location where the information bits are to be written to; said first read request packet including an operation specification code specifying a read function to be performed and a memory location where the information bits are read from, and said second read request packet including an operation specification code specifying a function to be performed and a memory mapped location where the information bits are read from; said memory mapped locations corresponding to inter-agent communications specifying an internal destination code of an agent and the functions desired of the specified agent; receiving means connected to said AP Bus for receiving a reply message packet on said AP Bus system, said reply message packet including a number of bus transmission slots, received sequentially and contiguously, each slot in said reply packet including operation specification code, data bits and control bits; said reply message packet containing an operation specification code and if requested data; message control means connected to said generating means and said receiving means said message control means including as a part of said message control means: means for queuing data in said write request packets, means responsive to said control bits in said read packets, and write packets for detecting a beginning and an end of each packet, means for decoding each said operation specification code to indicate the operation specified, means for establishing a pipeline for said request message packets, and said reply message packets generated on said AP Bus by said message generator, monitor means connected to said message control means and to said AP Bus system, for monitoring signals on said AP Bus system representative of said request packets, and reply packets on said bus, such that a request packet is prevented from entering said pipeline until a reply packet is received to make available a slot in said pipline, whereby request packets increase the length of said pipeline up to a predetermined number of request packets in said pipeline, and reply packets decrease the length of said pipeline; and means connected to said recognizing means, said generating means, said message control means and said receiving means, for arbitrating said signals on said Bus system representative of requests going onto said Bus system and said signals on said Bus system representative of replies received on said Bus, to enable said message control means to insert a reply packet associated with a particular request packet in the pipeline position of said recognized request packet.

Claim 5

The combination as set forth in claim 1, wherein said monitor means includes: reply monitor means including means for maintaining a queue of reply packets in the same order as the associated request packets; means for informing a replying unit when it is time to reply; and means for informing a requesting unit when an associated reply packet is to be received.

Claim 6

The combination as set forth in claim 2, wherein said monitor means includes: reply monitor means including means for maintaining a queue of reply packets in the same order as the associated request packets, means for informing a replying agent when it is time to reply and means for informing a requesting agent when an associated reply packet is to be received.

Claim 7

The combination as set forth in claim 4, further comprising: re-ordering means connected to said message control means, said generating means and said receiving means to enable said message control means to change the pipeline position which the reply packet associated with a particular request packet is inserted on the Advanced Processor Bus.

Claim 8

The combination as set forth in claim 1, further comprising: means connected to said monitor means and said message controller means, for arbitrating said signals on said Advanced Processor Bus representative of requests from said Advanced Processor Bus, and signals on said Advanced Processor Bus representative of replies received from said Advanced Processor Bus, to thereby enable said message controller means to insert a reply packet associated with a particular request packet in the pipeline position of said request packet.

Claim 9

The combination set forth in claim 6, further comprising re-ordering means connected to said monitor means and said pipeline queue means for changing the order that the reply message packets are communicated onto said bus system by deferring the use of the next available slot in the pipeline to a reply of lower priority within the pipeline queue, changing the order of the reply message packets in the pipeline.

Claim 10

The combination as set forth in claim 7, wherein said means for generating packets includes: means for generating on said AP Bus a write-request packet and a read-request packet, said write-request packet including an operation specification code specifying an operation desired, a memory mapped address, or an address specifying a physical memory location and write data, said read-request packet including an operating specification code specifying an operation desired, a memory mapped address, or an address specifying a physical memory location; and wherein said message controller means further comprises: means for queuing data in said write request packet; means responsive to said control bits in said read and write packets for detecting the start and end of a packet; and, means for decoding said operation specification code to provide an indication of a function.

Claim 11

The combination as set forth in claim 7, further comprising: means connected to said monitor means and said message controller means, for arbitrating said requests onto said bus and said replies received from said bus, to thereby enable said message controller means to insert a reply to a particular request in the pipeline queue at a position in said pipeline queue corresponding to the request message packet that is associated with said particular reply message packet.

Claim 12

The combination as set forth in claim 7, wherein said means for generating packets includes: means for generating on said AP Bus a write-request packet and a read-request packet, said write-request packet including an operation specification code specifying a function desired, a memory mapped address or address specifying a physical memory location, and write data, said read-request packet including an operation specification code specifying a function desired, and an address specifying a physical memory location; and wherein said message controller means further comprises: means for queuing data in said write request packet; means responsive to said control bits in said read and write packets for detecting the start and end of a packet; and means for decoding said operation specification code to provide an indication of a function.

Claim 13

The combination as set forth in claim 7, wherein said means for generating packets includes: means for generating on said bus a write-request packet and a read-request packet, said write-request packet including an operation specification code specifying an operation desired, a memory mapped address or an address specifying a physical memory location; and write data, said read-request packet including an operation specification code specifying a function desired, a memory mapped address, or an address specifying a physical memory location; and wherein said message controller means further comprises: means for queuing data in said write request packet; means responsive to said control bits in said read and write packets for detecting the start and end of a packet; and means for decoding said operation specification code to provide an indication of an operation.

Claim 14

The combination as set forth in claim 5, further comprising: means connected to said monitor means and said message controller means, for arbitrating said requests onto said AP Bus and said replies received from said AP Bus, to thereby enable said message controller means to insert a reply to a particular request in the pipeline queue at a position in said pipeline queue corresponding to the request message packet that is associated with said particular reply message packet.

Claim 15

The combination as set forth in claim 5, wherein said means for generating packets includes: means for generating on said AP Bus a write-request packet and a read-request packet, said write-request packet including an operation specification code specifying an operation desired, a memory mapped address, or an address specifying a physical memory location and write data, said read-request packet including an operation specification code specifying an operation desired, a memory mapped address, or an address specifying a physical memory location; and wherein said message controller means further comprises: means for queuing data in said write request packet; means responsive to said control bits in said read and write packets for detecting the start and end of a packet; and means for decoding said operation specification code to provide an indication of an operation.

Claim 16

The combination as set forth in claim 5, wherein said means for generating packets includes: means for generating on said bus a write-request packet and a read-request packet, said write-request packet including an operation specification code specifying an operation desired, a memory mapped address, or an address specifying a physical memory location; and pipeline queue means for changing the order that the reply message packets are communicated onto said bus system by deferring the use of the next available slot in the pipline to a reply of lower priority within the pipeline queue, changing the order of the reply message packets in the pipeline.

Claim 17

The combination as set forth in claim 1, further comprising: means for initializing the Advanced Processor Bus system, including a data portion, for identifying each major unit of said AP Bus system and providing to each said major unit instructions as to processes to be performed.

Claim 18

The combination as set forth in claim 2, further comprising: means for initializing the Advanced Processor Bus system, including a data portion, for identifying each major unit of the system and providing to each said major unit instructions as to special processes to be performed.

Claim 19

The combination as set forth in claim 1, further comprising: means for aiding diagnostics connected to said message generator means, said interface logic means and said control signal means whereby a bus command can be given stopping the information on the AP Bus in place for one bus cycle and including the capacity to repetitively give said information stopping command.

Claim 20

The combination as set forth in claim 2, comprising: means for aiding diagnostics connected to said message generator means, said interface logic means and said control signal means whereby a bus command can be given stopping the information on the AP Bus in place for one bus cycle and including the capability to repetitvely give said information stopping command.