EP0364955A2
Expired / Lapsed
EP
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A label-switching and control interface for asynchronous fast-packet switching
Assignee: TIM SpA
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Filing: 1989-10-17
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Granted: —
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Expires: 2009-10-17
Abstract
Abstract A label-switching and control interface for asynchronous fast-packet switching consisting of a set of label-switching and cell-processing units controlled by a suitable control unit; said units operate at each multiplex level in real time thanks to a microprogrammed logic requiring the control processor intervention only at the connection set-up/release. Said units implement the low levels of the flow control algorithms necessary to conveniently exploit the advantages of said techniques. The label becomes indicative of a virtual circuit which is allotted only locally to the call, annulling thus the necessity of very extensive labels, while the parameters which characterize the connection which uses a particular label are stored in the unit itself. Each unit switches the label characterizing the connection on the node input multiplex, with that whereby it is characterized on the output multiplex and at the same time associates, with each cell, the information necessary to multiplex switching which is then carried out in a self-routing network; the cells processed in this way by each unit of the set are statistically multiplexed ifl an asynchronous way and sent to a connection network termination. Such a termination serves more asynchronous multiplexes, which can be at different frequency from each other and more particulary it is worth noticing that each label switching unit hasn't its own operating frequency, but automatically takes up that of the asynchronous multiplex it is connected to.
Inventors
- 👤 Carlo Demichelis
- 👤 Paolo Mattone
- 👤 Alessandro Zappalorto
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 09:51
CPC Classifications
H; H04; H04L; H04L49/00; H04L49/20; H04L49/201; H04L49/203; H04J; H04J3/00; H04J3/24; H04J3/247
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
155 words
A label-switching and control interface for asynchronous fast packet-switching, wherein the packets, or cells, relevant to different calls are forwarded, as they become available, on bidirectional asynchronous multiplexes (i1), characterized in that a plurality of said bidirectional asynchronous multiplexes are connected to the same number of blocks (TMA) carrying out fast cell processing and being connected to an input bus (b2) of a multiplex switching-network (NWD) under the control of an arbitrating circuit (ARB) and a first bus (b7), and to an output bus (b8) of the same network through a distribution circuit (DIS) and a second bus (b4), a common control circuit (CON) being connected through a third bus (b3) to each block (TMA), which control circuit accesses the switching network through a first connection (b5) and the same arbitrating circuit (ARB) and, vice versa, the network accesses the common control circuit (CON) through the same distributing circuit (DIS) and a second connection (b6).
Claim 2
Dependent Claim
155 words
A label-switching and control interface for asynchronous fast packet-switching, wherein the packets, or cells, relevant to different calls are forwarded, as they become available, on bidirectional asynchronous multiplexes (i1), characterized in that a plurality of said bidirectional asynchronous multiplexes are connected to the same number of blocks (TMA) carrying out fast cell processing and being connected to an input bus (b2) of a multiplex switching-network (NWD) under the control of an arbitrating circuit (ARB) and a first bus (b7), and to an output bus (b8) of the same network through a distribution circuit (DIS) and a second bus (b4), a common control circuit (CON) being connected through a third bus (b3) to each block (TMA), which control circuit accesses the switching network through a first connection (b5) and the same arbitrating circuit (ARB) and, vice versa, the network accesses the common control circuit (CON) through the same distributing circuit (DIS) and a second connection (b6).
Claim 3
Dependent Claim
169 words
A label-switching and control interface as claimed in claim 1, characterized in that said blocks (TMA) comprise an incoming section comprising: - circuits (SH1,RG1,RG2,CR1,FSM4,CT1) detecting cell locations in the data flow (i1); - circuits (RG3,MEM,LUM) separating datum cells from signalling, supervision, stuffing, auxiliary flow cells, carrying out label switching and adding self-routing code for the switching network (NWD); - circuits (FSM8,MU1,FI1,CF1,FI2,CF2) for controlling the forwarding of cell octets to a switching network and for the temporary storage in function of a service class; - circuits (LMP,MEM,CAB,F13,CF3) for storing cells for multipoint connections and for retransmission of the same cells for the requested number of times; - an arbitrating circuit (ARU) among the sources (FI1,FI2,FI3) of cells to be sent to the switching network; - a temporaneous memory (FI4,CF4) for the cells meant for a processor (TSP) and an interface (CM1,RG4, ABM,TR1) for the access to the memory (MEM) by the processor; - an interface (CUA,RG5) of an auxiliary output for the emission of the cells of the auxiliary flow.
Claim 4
Dependent Claim
107 words
A label-switching and control interface as claimed in claim 1 or 2, characterized in that said blocks (TMA) comprise a microprogrammed logic consisting of: - an arithmetic-logic unit (ALU8) with input and output registers (RGA,RGB,ACC) connected to an internal bus (22) through multiplexing and demultiplexing circuits (MXA,MXB,DR3,DR4,DR5,DR6); - registers (RGC,RGD,RGE) for particular operands connected to an output bus (21) of the memory (MEM); - a microprogrammed memory (ROM), a relevant register (RPL) and a sequencing circuit (SEQ) with a multiplexer for conditioned jumps (MXS) and a multiplexer for bits under test (MXT); - a register (RAD) for the temporary storage of the label of the processed cell.
Claim 5
Dependent Claim
109 words
A label-switching and control interface as claimed in any of claims 1 to 3, characterized in that said blocks (TMA) comprise a parallel interface for translating input cells into messages for the processor and, vice versa, processor messages into cells to transmit on the line, which comprises: - a control circuit (FSMA) for the signalling towards the processor; - a data register (RG6, RG7, RG8, RG9); - a state register (FF3, FF4, FF5, FF6, FF7, FF8); - a circuit (FSMB) for controlling the flow coming from the processor; - a data register towards the processor (RG11, RG12, RG13, RG14); - an addressing circuit (CM2, RG10) controlled by the processor.
Claim 6
Dependent Claim
198 words
A label-switching and control interface as claimed in any of claims 1 to 4, characterized in that said blocks (TMA) comprise a transmission section consisting of: - a temporary memory (FI6,CF6) for the cells arriving from the processor registers (RG11, RG12, RG13, RG14); - a temporary memory (F15,CF5) for the cells arriving from the switching network to be forwarded on the line, preceded by a circuit (MXR,RG19,RG20,PG1, LIN,CM3) which selects the cells meant for the block itself (TMA) and calculates the label redundancies; - a generator of stuffing cells and of supervision cells (ROM1,CTB,CRC,MXCV); - control circuits of transmission and arbitration (FSMU,CTSUP,CTX,FF9, FF10); - transmission circuits, comprising a register (RG15) for receiving the octets of the cells of the auxiliary flow, a register (RG16) for receiving the octets of the cells arriving from the processor through said temporary memory (FI6,CF6), a register (RG17) for receiving the supervision and stuffing cells arriving from said generator (MXCV) and a register (RG18) for receiving the data cells arriving from the switching network through said temporary memory (F15,CF5), a multiplexer (MXU) for receiving the outputs of said registers and a shift register (SH2) for the transmission of the octets on the line.
Claim 7
Dependent Claim
139 words
A label-switching and control interface as claimed in any of claims 1 to 5, characterized in that said arbitrating circuit (ARB) comprises: - logic circuits (RMR1,RMR2,RG25) for receiving the request of forwarding the cells to the switching network by present blocks (TMA) and by the processor, and for the emission of the corresponding enablings according to an arbitrating algorithm; - a temporary memory circuit (FI7,CF7,RG21) with functions of an interface between processor and switching network; - a temporary memory circuit (FI8,CF8,RG22,RG23,RG24) with functions of interface between the switching network and the processor and of control of the flow outgoing from the network, which unloads from the switching network possible cells non-accepted by present blocks (TMA) or by the processor; - a converter (LAD) for the conversion of the incoming and outgoing flows from parallel to series and vice versa.
References Cited (Backward Citations)
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