Semiconductor memory device

Claim 2

A semiconductor memory device comprising: a row decoder (11) operative to receive a row address signal to decode said row address signal to output it as a row decoded signal; a latch circuit (12) operative to latch said row decoded signal from said row decoder (11) in synchronism with a synchronizing signal to drive one of a plurality of word lines (13) by said latched row decoded signal; and a memory cell array including a plurality of memory cells connected to said plurality of word lines (13), respectively, each memory cell being operative to carry out input/output operation of data when a word line (13) to which said each memory cell is connected is driven.

Claim 3

A semiconductor memory device comprising: a master latch circuit (12A) operative to receive a row address signal to latch said row address signal at the first half of one cycle of a synchronizing signal, and to output said row address signal as it is at the latter half of one cycle of said synchronizing signal; a row decoder (11) operative to receive the row address signal outputted from said master latch circuit (12A) to decode it into a row decoded signal, to thus output said row decoded signal; a slave latch circuit (12B) operative to receive the row decoded signal outputted from said row decoder (11) to latch said row decoded signal at the latter half of one cycle of said synchronizing signal, and to output said row decoded signal as it is at the first half of one cycle of said synchronizing signal, to thus drive one of a plurality of word lines; and a memory cell array including a plurality of memory cells connected to said word lines (13), respectively, each memory cell being operative to carry out input/output operation of data when a word line (13) to which said each memory cell is connected is driven.

Claim 4

A semiconductor memory device comprising: a master latch circuit (12A) operative to receive a row address signal to latch said row address signal at the first half of one cycle of a synchronizing signal, and to output said row address signal as it is at the latter half of one cycle of said synchronizing signal; a row decoder (11) operative to receive the row address signal outputted from said master latch circuit (12A) to decode it into a row decoded signal, to thus output said row decoded signal; a slave latch circuit (12B) operative to receive the row decoded signal outputted from said row decoder (11) to latch said row decoded signal at the latter half of one cycle of said synchronizing signal, and to output said row decoded signal as it is at the first half of one cycle of said synchronizing signal, to thus drive one of a plurality of word lines; and a memory cell array including a plurality of memory cells connected to said word lines (13), respectively, each memory cell being operative to carry out input/output operation of data when a word line (13) to which said each memory cell is connected is driven.

Claim 5

A semiconductor memory device comprising: a row decoder (11) operative to receive a row address signal to decode said row address signal to output it as a row decoded signal; a latch circuit (12) operative to latch the row decoded signal from said row decoder (11) in synchronism with a synchronizing signal, to thus drive a main word line (MWL); a section decoder (25) operative to receive a section address signal to decode said section address signal to output it as a section decoded signal; a latch circuit (26) operative to latch the section decoded signal from said section decoder (25) in synchronism with said synchronizing signal, to thus drive a section select line (SS); a plurality of logic circuits (28) for performing a logic operation between said main word line (MWL) and said section select line (SS) wherein when said main word line (MWL) and said section select line (SS) are both in a drive state, each logic circuit is operative to output a section word line drive signal for driving one of said plurality of section word lines (SWL); and a memory cell array (14) including a plurality of memory cells connected to said section word lines (SWL), respectively, each memory cell being operative to carry out input/output operation of data when a section word line (SWL) to which said each memory cell is connected is driven.

Claim 6

A semiconductor memory device comprising: a row decoder (11) operative to receive a row address signal to decode said row address signal to output it as a row decoded signal; a latch circuit (12) operative to latch the row decoded signal from said row decoder (11) in synchronism with a synchronizing signal, to thus drive a main word line (MWL); a section decoder (25) operative to receive a section address signal to decode said section address signal to output it as a section decoded signal; a latch circuit (26) operative to latch the section decoded signal from said section decoder (25) in synchronism with said synchronizing signal, to thus drive a section select line (SS); a plurality of logic circuits (28) for performing a logic operation between said main word line (MWL) and said section select line (SS) wherein when said main word line (MWL) and said section select line (SS) are both in a drive state, each logic circuit is operative to output a section word line drive signal for driving one of said plurality of section word lines (SWL); and a memory cell array (14) including a plurality of memory cells connected to said section word lines (SWL), respectively, each memory cell being operative to carry out input/output operation of data when a section word line (SWL) to which said each memory cell is connected is driven.

Claim 7

A semiconductor memory device comprising: a master latch circuit (12A) operative to receive a row address signal to latch said row address signal at the first half of one cycle of a synchronizing signal, and to output said row address signal as it is at the latter half of one cycle of said synchronizing signal; a row decoder (11) operative to receive the row address signal outputted from said master latch circuit (12A) to decode said row address signal into a row decoded signal to output said row decoded signal; a slave latch circuit (12B) operative to receive the row decoded signal outputted from said row decoder (11) to latch said row decoded signal at the latter half of one cycle of said synchronizing signal, and to output said row decoded signal as it is at the first half of one cycle of said synchronizing signal, to thus drive one of main word lines (MWL); a master latch circuit (26A) operative to receive a section address signal to latch said section address signal at the first half of one cycle of said synchronizing signal, and to output said section address signal as it is at the latter half of one cycle of said synchronizing signal; a section decoder (25) operative to receive the section address signal outputted from said master latch circuit (26A) to decode said section address signal into a section decoded signal to output said section decoded signal; a slave latch circuit (26B) operative to receive the section decoded signal outputted from said section decoder (25) to latch said section decoded signal at the latter half of one cycle of said synchronizing signal, and to output said section decoded signal as it is at the first half of one cycle of said synchronizing signal, to thus drive one of section select lines (SS); a plurality of logic circuits (28) for performing a logic operation between said main word lines (MWL) and said section select lines (SS) wherein when said main word lines (MWL) and said section select lines are both in a drive state, each logic circuit is operative to output a section word line drive signal for driving one of said plurality of section word lines (SWL); and a memory cell array (14) including a plurality of memory cells connected to said section word lines (SWL), respectively, each memory cell being operative to carry out input/output operation of data when a section word line (SWL) to which said each memory cell is connected is driven.

Claim 8

A semiconductor memory device comprising: a master latch circuit (12A) operative to receive a row address signal to latch said row address signal at the first half of one cycle of a synchronizing signal, and to output said row address signal as it is at the latter half of one cycle of said synchronizing signal; a row decoder (11) operative to receive the row address signal outputted from said master latch circuit (12A) to decode said row address signal into a row decoded signal to output said row decoded signal; a slave latch circuit (12B) operative to receive the row decoded signal outputted from said row decoder (11) to latch said row decoded signal at the latter half of one cycle of said synchronizing signal, and to output said row decoded signal as it is at the first half of one cycle of said synchronizing signal, to thus drive one of main word lines (MWL); a master latch circuit (26A) operative to receive a section address signal to latch said section address signal at the first half of one cycle of said synchronizing signal, and to output said section address signal as it is at the latter half of one cycle of said synchronizing signal; a section decoder (25) operative to receive the section address signal outputted from said master latch circuit (26A) to decode said section address signal into a section decoded signal to output said section decoded signal; a slave latch circuit (26B) operative to receive the section decoded signal outputted from said section decoder (25) to latch said section decoded signal at the latter half of one cycle of said synchronizing signal, and to output said section decoded signal as it is at the first half of one cycle of said synchronizing signal, to thus drive one of section select lines (SS); a plurality of logic circuits (28) for performing a logic operation between said main word lines (MWL) and said section select lines (SS) wherein when said main word lines (MWL) and said section select lines are both in a drive state, each logic circuit is operative to output a section word line drive signal for driving one of said plurality of section word lines (SWL); and a memory cell array (14) including a plurality of memory cells connected to said section word lines (SWL), respectively, each memory cell being operative to carry out input/output operation of data when a section word line (SWL) to which said each memory cell is connected is driven.

Claim 10

A device as set forth in claim 5, which further comprises: a column decoder (16) operative to receive a column address signal to decode said column address signal to output it as a column decoded signal; and a latch circuit (17) operative to latch said column decoded signal from said column decoder (16) in synchronism with a synchronizing signal to select one of a plurality of bit lines (18) by the latched column decoded signal; a memory cell connected to said selected bit line (18) of the memory cells connected to said driven word line (13) being subjected to input/output operation of said data.

Claim 11

A device as set forth in claim 5, which further comprises: a latch circuit (17) operative to receive a column address signal to latch said column address signal in synchronism with a synchronizing signal; and a column decoder (16) operative to receive the column address signal from said latch circuit (17) to decode said column address signal to output it as a column decoded signal, to thus select one of a plurality of bit lines (18); a memory cell connected to said selected bit line (18) of the memory cells connected to said driven word line (13) being subjected to input/output operation of said data.

Claim 12

A device as set forth in claim 5, which further comprises: a master latch circuit (17A) operative to receive a column address signal to latch said column address signal at the first half of one cycle of the synchronizing signal, and to output said column address signal as it is at the latter half of one cycle of said synchronizing signal; a column decoder (16) operative to receive a column address signal outputted from said master latch circuit (17A) to decode said column address signal into a column decoded signal, to thus output said column decoded signal; and a slave latch circuit (17B) operative to receive the column decoded signal outputted from said column decoder (16) to latch said column decoded signal at the latter half of one cycle of said synchronizing signal, and output said column decoded signal as it is at the first half of one cycle of said synchronizing signal, to thus select one of said plurality of bit lines (18); a memory cell connected to said selected bit line (18) of the memory cells connected to said driven word line (13) being subjected to input/output operation of said data.

Claim 13

A device as set forth in claim 5, which further comprises: a column decoder (16) operative to receive a column address signal to decode said column address signal to output it as a column decoded signal; and a latch circuit (17) operative to latch the column decoded signal from said column decoder (16) in synchronism with a synchronizing signal to select one of said plurality of bit lines (18); a memory cell connected to said selected bit line (18) of the memory cells connected to said driven section word line (SWL) being subjected to input/output operation of said data.

Claim 14

A device as set forth in claim 5, which further comprises: a latch circuit (17) operative to receive a column address signal to latch said column address signal in synchronism with a synchronizing signal; and a column decoder (16) operative to receive the column address signal from said latch circuit (17) to decode said column address signal to output it as a column decoded signal, to thus select one of said plurality of bit lines (18); a memory cell connected to said selected bit line (18) of the memory cells connected to said driven section word line (SWL) being subjected to input/output operation of said data.

Claim 15

A device as set forth in claim 5, which further comprises: a master latch circuit (17A) operative to receive a column address signal to latch said column address signal at the first half of one cycle of said synchronizing signal, and to output said column address signal as it is at the latter half of one cycle of said synchronizing signal; a column decoder (16) operative to receive a column address signal outputted from said master latch circuit (17A) to decode it into a column decoded signal to output said column decoded signal; and a slave latch circuit (17B) operative to receive the column decoded signal outputted from said column decoder (16) to latch said column decoded signal at the latter half of one cycle of said synchronizing signal, and to output said column decoded signal as it is at the first half of one cycle of said synchronizing signal; a memory cell connected to said selected bit line (18) of the memory cells connected to said driven section word line (SWL) being subjected to input/output operation of said data.

Claim 16

A device as set forth in claim 1, which further comprises a data processing unit (30) having an address generation circuit (26) for outputting said row address signal, said address generation circuit (26) being connected to said row decoder (11) through a data bus (28).

Claim 17

A device as set forth in claim 6, which further comprises a data processing unit (30) having an address generation circuit (26) for outputting said row address signal and said column address signal, said address generation circuit (26) being connected to said row decoder (11) and said column decoder (16) through a data bus (28).

Claim 18

A device as set forth in claim 3, which further comprises a data processing unit (30) having an address generation circuit (26) for outputting said row address signal and said section address signal, said address generation circuit (26) being connected to said row decoder (11) and said column decoder (25) through a data bus (28).

Claim 19

A device as set forth in claim 9, which further comprises a data processing unit (30) having an address generation circuit (26) for outputting said row address signal, said section address signal, and said column address signal, said address generation circuit (26) being connected to said row decoder (11), said section decoder (25) and said column decoder (16) through a data bus (28).

Claim 20

A device as set forth in claim 2, which further comprises a data processing unit (30) having an address generation circuit (26) for outputting said row address signal, said address generation circuit (26) being connected to said master latch circuit (12A) through a data bus (28).

Claim 21

A device as set forth in claim 8, which further comprises a data processing unit (30) having an address generation circuit (26) for outputting said row address signal, and said column address signal, said address generation circuit (26) being connected to said rerspective two master latch circuits (12A, 17A) on the row and column sides through a data bus (28).

Claim 22

A device as set forth in claim 4, which further comprises a data processing unit (30) having an address generation circuit (26) for outputting said row address signal, and said section address signal, said address generation circuit (26) being connected to said respective two master latch circuits (12A, 26A) on the row and section sides through a data bus (28).

Claim 23

A device as set forth in claim 11, which further comprises a data processing unit (30) having an address generation circuit (26) for outputting said row address signal, said section address signal, and said column address signal, said address generation circuit (26) being connected to said respective three master latches (12A, 26A, 17A) on the row, section and column sides through a data bus (28).