Integrated-circuit configuration having fast local access time

Claim 2

A memory circuit presenting data at output terminals in response to receiving address information and control signals, said memory circuit comprising: an array of memory cells capable of storing data; sense amplifiers connected to said array of memory cells; and a line buffer of data latches connected between said sense amplifiers and said output terminals, each data latch being connected between one sense amplifier and one data terminal, in response to receipt of certain address information and control signals, said memory circuit transmitting data from said line buffer of data latches to said output terminals and, in receipt of other address information, said memory circuit transmitting data from said memory array through said sense amplifiers to said line buffer of data latches for later transmission to said output terminals.

Claim 3

The memory circuit of Claim 1 in which said data latches are arranged in selectable groups and said address information selects one group of said data latches for transmitting data to said output terminals.

Claim 4

The memory circuit of Claim 1 including control circuits connected to said address information, said control signals, said sense amplifiers and said line buffer of data latches for storing the addresses of data stored in said line buffer and comparing said received address information to said stored addresses in determining whether to transmit data in said data latches to said output terminals and transmitting data from said memory cells to said data latches for later transmission to said output terminals.

Claim 5

The memory circuit of Claim 3 in which said control circuits transmit a MISS signal upon said address information indicates data not in said line buffer of data latches.

Claim 6

The memory circuit of Claim 3 in which said control circuits include a reset circuit for transmitting data from said array through said sense amplifiers to said data latches upon power up.

Claim 7

The memory circuit of Claim 1 in which said memory cells are non-volatile.

Claim 8

The memory circuit of Claim 1 in which'said memory cells are electrically-programmable, read-only-memory.

Claim 9

The memory circuit of Claim 1 in which said array of memory cells are arranged in rows and columns, said columns presenting plural words of data and said address information addressing individual ones of said words of data in said line buffer.

Claim 10

The memory circuit of Claim 8 in which said data latches are arranged in 16 words of data with 16 bits in each word.

Claim 11

A processor system comprising: a processor presenting address signals on parallel address terminals and control signals on control terminals for receiving requested data on parallel data terminals; and a memory circuit connected to said address terminals, control terminals and data terminals, said memory circuits including an array of memory cells capable of storing data, sense amplifiers connected to said array of memory cells and a line buffer of data latches connected between said sense amplifiers and said output terminals, each data latch being connected between a sense amplifier and a data terminal, in response to receipt of certain address information and control signals, said memory circuit transmitting data from said line buffer of data latches to said output terminals and, in receipt of other address information, said memory circuit transmitting data from said memory array through said sense amplifiers to said line buffer of data latches for later transmission to said output terminals.

Claim 12

A processor system comprising: a processor presenting address signals on parallel address terminals and control signals on control terminals for receiving requested data on parallel data terminals; and a memory circuit connected to said address terminals, control terminals and data terminals, said memory circuits including an array of memory cells capable of storing data, sense amplifiers connected to said array of memory cells and a line buffer of data latches connected between said sense amplifiers and said output terminals, each data latch being connected between a sense amplifier and a data terminal, in response to receipt of certain address information and control signals, said memory circuit transmitting data from said line buffer of data latches to said output terminals and, in receipt of other address information, said memory circuit transmitting data from said memory array through said sense amplifiers to said line buffer of data latches for later transmission to said output terminals.

Claim 13

The memory circuit of Claim 10 in which said data latches are arranged in selectable groups and said address signals select one group of said data latches for transmitting data to said data terminals.

Claim 14

The memory circuit of Claim 10 in which said memory circuit includes control circuits connected to said address terminals, said control terminals, said sense amplifiers, and said line buffer of data latches for storing the addresses of data stored in said line buffer and comparing said received address signals to said stored addresses in determining whether to transmit data in said data latches to said output terminals and transmitting data from said memory cells to said data latches for later transmission to said output terminals.

Claim 15

The memory circuit of Claim 12 in which said control circuits transmit a MISS signal to said control terminals upon said address signals indicating data not in said line buffer of data latches.

Claim 16

The memory circuit of Claim 12 in which said control circuits include a reset circuit for transmitting data from said array through said sense amplifiers to said data latches upon power up.

Claim 17

The memory circuit of Claim 10 in which said memory cells are non-volatile.

Claim 18

The memory circuit of Claim 10 in which said memory cells are electrically-programmable, read-only-memory.

Claim 19

The memory circuit of Claim 10 in which said array of memory cells are arranged in rows and columns, said columns presenting plural words of data and said address signals addressing individual ones of said words of data in said line buffer.

Claim 20

The memory circuit of Claim 17 in which said data latches are arranged in 16 words of data with 16 bits in each word.