EP0387644A1
Expired / Lapsed
EP
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Multiprocessor system with global data replication and two levels of address translation units
Assignee: Bull HN Information Systems Italia SpA
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Filing: 1990-03-03
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Granted: —
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Expires: 2010-03-03
Abstract
Abstract In a multiprocessor system having global data replication in each of the local memories, each associated with one of the processors, the global data allocation in the several local memories is performed by translating global data logical addresses in addresses conventionally defined as real, the translation being performed by a first translation unit associated to and managed bythe processor which generates the global data, the first translation being followed by the translation of the real address in a physical address generally differing for each local memory and performed by a plurality of translation unis, each associated with a one of the local memories and managed by the processor associated with that local memory.
Inventors
- 👤 Angelo Casamatta
- 👤 Calogero Mantellina
- 👤 Daniele Zanzottera
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-24 18:11
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/0223; G06F12/0284; G06F12/06; G06F12/0646; G06F12/0692; G06F12/08; G06F12/10; G06F12/1027
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
213 words
1) Multiprocessor system with global data replication and two levels of address translation units, wherein each of a plurality of processors (1,2,3,4) has a local memory (8,14) associated therewith, each processor has access to its own local memory through a local bus and each processor has access to the local memory of another processor through its own local bus (11,28) and a system bus (5), where further global data used by more than one processor are replicated and stored in each one of said local memories, characterized by that said system comprises a first address translation unit (9,17) in each one of said processors,associated therewith and accessible only from the associated processor, for converting logical addresses of global data generated by the associated processor in real addresses each containing a bit code which identifies it as real,a second address translation unit (8B,14B) in each of said processors, associated with the local memory thereof and accessible from by said processor and from said system bus, for converting said real addresses, received from any one of said first translation units in a physical address input as address to the local memory associated thereto and logical means (40) for detecting said real addresses and for activating said second unit only upon detection of said real addresses.
Claim 2
Dependent Claim
213 words
1) Multiprocessor system with global data replication and two levels of address translation units, wherein each of a plurality of processors (1,2,3,4) has a local memory (8,14) associated therewith, each processor has access to its own local memory through a local bus and each processor has access to the local memory of another processor through its own local bus (11,28) and a system bus (5), where further global data used by more than one processor are replicated and stored in each one of said local memories, characterized by that said system comprises a first address translation unit (9,17) in each one of said processors,associated therewith and accessible only from the associated processor, for converting logical addresses of global data generated by the associated processor in real addresses each containing a bit code which identifies it as real,a second address translation unit (8B,14B) in each of said processors, associated with the local memory thereof and accessible from by said processor and from said system bus, for converting said real addresses, received from any one of said first translation units in a physical address input as address to the local memory associated thereto and logical means (40) for detecting said real addresses and for activating said second unit only upon detection of said real addresses.
Claim 3
Dependent Claim
85 words
2) System as in claim 1, comprising means (5,10,29) for transferring real addresses generated by any one of said first translation units, in case of write operation, to all said second translation units, whereby said real addresses generated by the first translation unit associated with one processor is sent through said system bus to each one of the other processors and converted by each one of said second translation units in a plurality of physical addresses each one for addressing one of said local memories.
Claim 4
Dependent Claim
17 words
3) Multiprocessor system as in claim 1 where said second translation units are static random access memories.
Claim 5
Dependent Claim
67 words
4) Multiprocessor system as in claim 3 where at least one of said local memories comprises a plurality of modules individually selectable for a read/write operation, by a selection code obtained from a field of a physical address and at least the second translation unit associated with said one local memory translates said received real address in a physical address and jointly in a module selection code.
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