EP0396484A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Solder column connection
Assignee: International Business Machines Corp
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Filing: 1990-03-27
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Granted: —
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Expires: 2010-03-27
Abstract
Abstract A low cost process for fabricating solder column interconnections for an electronic package is described. The process includes the steps of filling an array of pin holes in a pin mold (14) with a lead/tin solder, which array of pin holes is in substantial registration with the array of conductive pads (12) on one side of a chip carrier (2); heating the lead/tin solder in the pin mold such that the solder becomes molten and coalesces with the array of conductive pads of the chip carrier, thereby forming an array of miniature pins (4) bonded to the array of conductive pads of the chip carrier; joining circuit components to the other side of the chip carrier; and reflowing an eutectic lead/tin solder paste screened to the corresponding array of conductive pads of a circuit board to bond the free ends of the array of miniature pins of the carrier to the corresponding array of conductive pads, thereby forming the solder column connections between the chip carrier and the circuit board. The process is suitable for mass production of reliable, high-density electrical inter-connections between a chip carrier and a supporting circuit board.
Inventors
- 👤 John Richard Behun
- 👤 William Robert Miller
- 👤 Bert Harrison Newman
- 👤 Edward Louis Yankowski
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 03:01
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/30; H05K3/32; H05K3/34; H05K3/341; H05K3/3431; H05K3/3436; H05K3/3465; H05K3/3478; H05K2201/00; H05K2201/03; H05K2201/0332; H05K2201/0364; H05K2201/0379; H05K2201/10; H05K2201/10613; H05K2201/10621; H05K2201/10734; H05K2201/10954; H05K2201/10992; H05K2203/00; H05K2203/04; H05K2203/041; H05K2203/0415; H05K2203/043; H05K2203/05; H05K2203/0548; H05K2203/0557; H10; H10W; H10W90/00; H10W90/701; H10W90/721; H10W90/724; Y; Y02; Y02P; Y02P70/00; Y02P70/50; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49147; Y10T29/49149
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
244 words
1 . A process for fabricating a circuit package comprising the steps of : providing a carrier (2) having on one side thereof a first array of conductive pads (12); placing a pin mold (14) having a corresponding array of pin holes (16) in alignment with said carrier such that said corresponding array of pin holes is in substantial registration with said first array of conductive pads; filling said array of pin holes in said pin mold with a first solder having a given melting point; heating said first solder in said pin mold such that said first solder becomes molten and coalesces with said first array of conductive pads, thereby forming an array of miniature pins (4) bonded to said first array of conductive pads of said carrier, and said process being characterized in that it further comprises the steps of : placing a supporting substrate (6) having on one side thereof a second corresponding array of conductive pads (22), screened with a second solder having a melting point substantially lower than said given melting point, in alignment with said carrier such that said second corresponding array of conductive pads is in substantial registration with the free ends of said array of miniature pins of said carrier; and reflowing said second solder to bond the free ends of said array of miniature pins to said second corresponding array of conductive pads, thereby forming solder column connections between said carrier and said supporting substrate.
Claim 2
Dependent Claim
244 words
1 . A process for fabricating a circuit package comprising the steps of : providing a carrier (2) having on one side thereof a first array of conductive pads (12); placing a pin mold (14) having a corresponding array of pin holes (16) in alignment with said carrier such that said corresponding array of pin holes is in substantial registration with said first array of conductive pads; filling said array of pin holes in said pin mold with a first solder having a given melting point; heating said first solder in said pin mold such that said first solder becomes molten and coalesces with said first array of conductive pads, thereby forming an array of miniature pins (4) bonded to said first array of conductive pads of said carrier, and said process being characterized in that it further comprises the steps of : placing a supporting substrate (6) having on one side thereof a second corresponding array of conductive pads (22), screened with a second solder having a melting point substantially lower than said given melting point, in alignment with said carrier such that said second corresponding array of conductive pads is in substantial registration with the free ends of said array of miniature pins of said carrier; and reflowing said second solder to bond the free ends of said array of miniature pins to said second corresponding array of conductive pads, thereby forming solder column connections between said carrier and said supporting substrate.
Claim 3
Dependent Claim
27 words
A process for fabricating a circuit package as set forth in claim 1, wherein said first solder and said second solder are IVa - Va metal alloys.
Claim 4
Dependent Claim
21 words
A process for fabricating a circuit package as set forth in claim 2, wherein said first solder is a lead/tin solder.
Claim 5
Dependent Claim
44 words
A process for fabricating a circuit package as set forth in claim 3, wherein said first solder is a lead/tin solder with a composition, by weight, of lead in the range of 97% - 85%, and tin in the range of 3% - 15%.
Claim 6
Dependent Claim
24 words
A process for fabricating a circuit package as set forth in claim 2, 3 or 4, wherein set second solder is a lead/tin solder.
Claim 7
Dependent Claim
44 words
A process for fabricating a circuit package as set forth in claim 5, wherein said second solder is a lead/tin solder with a composition, by weight, of lead in the range of 30% - 45%, and tin in the range of 70% - 55%.
Claim 8
Dependent Claim
23 words
A process for fabricating a circuit package as set forth in claim 5 or 6, wherein said second solder is a eutectic mixture.
Claim 9
Dependent Claim
31 words
A process for fabricating a circuit package according to any one of the preceding claims, wherein said carrier is a ceramic carrier, and said supporting substrate is an organic circuit board.
Claim 10
Dependent Claim
35 words
A process for fabricating a circuit package according to any one of the preceding claims, further including the step of cutting said array of miniature pins to a substantial uniform height before said reflowing step.
Claim 11
Dependent Claim
30 words
A process according to any one of the preceding claims further including the step of joining circuit components to the other side of said carrier, prior to said placing step.
Claim 12
Dependent Claim
42 words
a process for fabricating a circuit package as set forth in claim 10, wherein said step of joining circuit components is accomplished by using a lead/tin solder having a composition, by weight, of 97% - 95% lead and 3% - 5% tin.
References Cited (Backward Citations)
No citation records indexed.
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