Method and apparatus for data transfer between processor elements

Claim 2

1 A method of data transfer for a processing element which is formed of a processor, a memory and a data transfer controller respectively mutually coupled to a data bus, the method comprising: (a) supplying a transfer command signal to the data transfer controller, for designating that a datum is to be transferred out of the processing element; (b) concurrent with step (a), supplying the datum to the data bus under the control of the processor; and (c) initiating the transfer of the datum, under the control of the data transfer controller, in response to the transfer command signal.

Claim 3

A method of data transfer according to claim 1, in which the datum is supplied to the data bus while the memory is being accessed by the processor.

Claim 4

A method of data transfer according to claim 2, in which a program that is executed by the processor includes instructions for designating memory access operations by the processor which are to be executed concurrently with generation of respective ones of the transfer command signals, and instructions for designating only memory access operations by the processor.

Claim 5

A method of data transfer according to claim 1, and further comprising a step of registering the memory address of each datum that is to be transferred, and, when an internal condition of the data transfer controller does not permit transfer of one or more data to be initiated, registering the number of data for which transfer has not yet been initiated, and thereafter executing an equal number of successive memory read operations using the registered addresses and initiating transfer of these data, when subsequently permitted by that internal condition and when the data bus is released by the processor

Claim 6

In a processing element formed of at least a processor, a memory and a data transfer controller respectively coupled to a data bus and address bus, the improvement whereby the data transfer controller comprises: read address registering means (41) for holding a value of memory address in which is stored a datum corresponding to a most recently issued transfer command signal from the processor, and means for updating the address value each time that a transfer command signal is issued by the processor; and status registering means (8) for maintaining a count of a total number of transfer command signals issued by the processor for which respectively corresponding transfer command signal have not yet been initiated by the data transfer controller; in which, when a transfer command signal is issued by the processor while the data transfer controller is in an internal operating condition whereby initiation of data transfer is currently possible, the data transfer controller initiates the data transfer and advances the address value held in the read address registering means, whereas each time that a transfer command signal is issued by the processor while the data transfer controller is in an internal operating condition in which initiation of data transfer is not possible, the data transfer controller increments the count in the status registering means, and when initiation of data transfer by the data transfer controller subsequently becomes possible and control of the data bus is released by the processor, supplies successive address values from the read address registering means to execute read-­out from the memory of successive ones of the data for which transfer was designated while transfer initiation was not possible, and in which the data transfer controller advances the address value held in the read address registering means and decrements the count in the status registering means each time that such a memory read access is thus executed.

Claim 7

In a processing element formed of at least a processor, a memory and a data transfer controller respectively coupled to a data bus and address bus, the improvement whereby the data transfer controller comprises: read address registering means (41) for holding a value of memory address in which is stored a datum corresponding to a most recently issued transfer command signal from the processor, and means for updating the address value each time that a transfer command signal is issued by the processor; and status registering means (8) for maintaining a count of a total number of transfer command signals issued by the processor for which respectively corresponding transfer command signal have not yet been initiated by the data transfer controller; in which, when a transfer command signal is issued by the processor while the data transfer controller is in an internal operating condition whereby initiation of data transfer is currently possible, the data transfer controller initiates the data transfer and advances the address value held in the read address registering means, whereas each time that a transfer command signal is issued by the processor while the data transfer controller is in an internal operating condition in which initiation of data transfer is not possible, the data transfer controller increments the count in the status registering means, and when initiation of data transfer by the data transfer controller subsequently becomes possible and control of the data bus is released by the processor, supplies successive address values from the read address registering means to execute read-­out from the memory of successive ones of the data for which transfer was designated while transfer initiation was not possible, and in which the data transfer controller advances the address value held in the read address registering means and decrements the count in the status registering means each time that such a memory read access is thus executed.

Claim 8

A processing element according to claim 5, in which the data transfer controller comprises: means (35d, 35e, 35a) for detecting a first condition in which a transfer command signal has been issued by the processor while the status registering means contains an initial value and the data transfer controller internal condition permits initiation of a data transfer operation, and for responding to detection of the first condition by generating a signal (15) for incrementing the status registering means from the initial value, and by generating a first address advancement signal (37a) for advancing the address value held in the read address registering means and a signal (12) for initiating a data transfer; means (35b) for detecting a second condition in which the status registering means contains a value other than the initial value, the data transfer controller internal condition permits initiation of a data transfer operation, and the data bus and address bus have been released by the processor, and for responding to detection of the second condition by generating a second address advancement signal (37b) for advancing the address value held in the read address registering means and initiating a data transfer operation, and a signal (16) for decrementing the contents of the status registering means, and for initiating a read access operation of the memory while supplying the contents of the read address registering means to the address bus.

Claim 9

A processing element which includes a processor a memory, and a data transfer controller respectively coupled to a data bus, in which the processor is configured to generate, concurrent with generation of a transfer command signal for designating to the data transfer controller that a datum is to be transferred from the processing element to an external system, control signals for executing a memory access for writing the datum into a predetermined address of the memory while the processor is supplying the datum to the data bus, or for reading the datum from a predetermined address of the memory to be supplied to the data bus, and in which the data transf er controller comprises: an output data buffer coupled to the data bus for transferring the datum to the external system; a status counter; a read address counter; and a control circuit; in which the control circuit controls the read address counter to maintain therein the address value of the datum which is currently designated to be transferred, and in which the control circuit responds to the transfer command signal by loading the datum from the data bus during the memory access by the processor and incrementing the address value in the read address counter, unless the output data buffer is currently full, and in which if the output data buffer is full, the control circuit responds to the transfer command signal by incrementing the status counter from a predetermined initial count value and subsequently, when the buffer ceases to be full and memory accessing by the processor has ceased, detecting that the value in the status counter is other than the initial count value and responding to that condition by generating control signals for reading out to the data bus the datum from the address held in the read address counter and for loading the datum into the output data buffer, while incrementing the read address counter and decrementing the status counter.

Claim 10

A processing element which includes a processor a memory, and a data transfer controller respectively coupled to a data bus, in which the processor is configured to generate, concurrent with generation of a transfer command signal for designating to the data transfer controller that a datum is to be transferred from the processing element to an external system, control signals for executing a memory access for writing the datum into a predetermined address of the memory while the processor is supplying the datum to the data bus, or for reading the datum from a predetermined address of the memory to be supplied to the data bus, and in which the data transf er controller comprises: an output data buffer coupled to the data bus for transferring the datum to the external system; a status counter; a read address counter; and a control circuit; in which the control circuit controls the read address counter to maintain therein the address value of the datum which is currently designated to be transferred, and in which the control circuit responds to the transfer command signal by loading the datum from the data bus during the memory access by the processor and incrementing the address value in the read address counter, unless the output data buffer is currently full, and in which if the output data buffer is full, the control circuit responds to the transfer command signal by incrementing the status counter from a predetermined initial count value and subsequently, when the buffer ceases to be full and memory accessing by the processor has ceased, detecting that the value in the status counter is other than the initial count value and responding to that condition by generating control signals for reading out to the data bus the datum from the address held in the read address counter and for loading the datum into the output data buffer, while incrementing the read address counter and decrementing the status counter.

Claim 11

A multiprocessor system comprising a plurality of processing elements interconnected by a network for mutual interchange of data, each processing element comprising a processor and a memory linked by a data bus, a data transfer controller, a first input/output port coupled between the data transfer controller and the data bus, and a second input/output port coupled between the data transfer controller and the network, in which when a datum is to be transferred from from the i th processing element to the j th processing element of the multiprocessor system, the processor of the i th processing element generates a transfer command signal while at the same time executing a memory access operation, the data transfer controller of the i th processing element responds to that transfer command signal by loading the datum into the first input/output port of the i th processing element while the datum is being transferred between the processor and memory of the i th processing element, and the datum is then transferred to the network from the second input/output port of the i th b processing element, and in which the data transfer controller of the j th processing element loads the datum into the second input/output port of the j th processing element from the network, and then transfers the datum from the first input/output port of the j th processing element to the memory of the j th processing element to be written therein.

Claim 12

A multiprocessor system comprising a plurality of processing elements interconnected by a network for mutual interchange of data, each processing element comprising a processor and a memory linked by a data bus, a data transfer controller, a first input/output port coupled between the data transfer controller and the data bus, and a second input/output port coupled between the data transfer controller and the network, in which when a datum is to be transferred from from the i th processing element to the j th processing element of the multiprocessor system, the processor of the i th processing element generates a transfer command signal while at the same time executing a memory access operation, the data transfer controller of the i th processing element responds to that transfer command signal by loading the datum into the first input/output port of the i th processing element while the datum is being transferred between the processor and memory of the i th processing element, and the datum is then transferred to the network from the second input/output port of the i th b processing element, and in which the data transfer controller of the j th processing element loads the datum into the second input/output port of the j th processing element from the network, and then transfers the datum from the first input/output port of the j th processing element to the memory of the j th processing element to be written therein.