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EP0410402A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

An automatic system for adjusting the output impedance of fast CMOS drivers

Assignee: Telecom Italia SpA
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Filing: 1990-07-25
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Granted: —
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Expires: 2010-07-25
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Abstract

Abstract An automatic system for adjusting the output impedance of fast CMOS drivers, wherein the output impedance of a plurality of slaved drivers is adjusted by a circuit for measuring and correcting mismatch between the output impedance of one of the drivers, taken as reference and dedicated to this aim, and the impedance at the input of a reference transmission line, equal to the lines connected to the other drivers. The measuring of the output impedance of the reference driver (DM) is indirectly effected by inserting at the reference driver input (2, 3) a clock signal and by periodically measuring the output on the reference transmission line (L) in correspondance with the positive half-period center. The measured voltage is sent to a comparator (CO) whereby it is compared with a reference level equal to half the maximum level present in the line under matching conditions and, according to the comparison result, a signal is supplied capable of charging or discharging a capacitor (C1), across whose terminals a voltage controlling the driver output impedance is available.

Inventors

  • 👤 Valter Bella
  • 👤 Franco Salerno
  • 👤 Mario Sartori

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-02 14:14
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/0264; H04L25/0278; H03; H03K; H03K19/00; H03K19/0005; H03K19/0175; H03K19/0185; H03K19/018585; H04L25/12; H04L25/028

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 318 words
An automatic system for adjusting the output impedance of fast CMOS drivers, wherein the output impedance of a plurality of slaved drivers (DS1...DSn) is controlled by a circuit for measuring and correcting mismatch between one of the drivers (DM), taken as reference and dedicated to this aim, and the impedance at the input of a reference trans-mission line (L), equal to lines (L1...Ln) connected to the other drivers, the output impedance adjustment of the reference driver (DM) being carried out by a comparator comparing the maximum voltage of a clock signal supplied by that reference driver (DM) at the input of the reference line (L) with a reference voltage equal to half the supply voltage of the output stages of the drivers and dependant on the result of the comparison said comparator supplies a current which periodically charges or discharges a capacitor (C1), so as to obtain across its terminals a control voltage for the driver impedance, characterized in that a first clock signal is sent to the input (2, 3) of said reference driver (DM) producing a periodic signal on said reference line (L) terminated by a resistance (R) equal to its characteristic impedance and said periodic signal present at the reference line input is compared with said reference voltage in a threshold comparator (CO) in correspondence with the transitions of a second clock signal (on 6) with a frequency equal to that of the first clock signal, but in quadrature so as to carry out the comparison at the center of the half-period wherein the voltage at the input of the reference line (L) is maximum, the comparison result being used to charge or discharge the capacitor (C1), whose voltage is applied to the inputs of a plurality of buffer amplifiers, one (BU) of which controls the output impedance of the reference driver (DM) and the others (BU1...BUn) the output impedances of the slaved drivers (DS1...DSn).
Claim 2
Dependent Claim 318 words
An automatic system for adjusting the output impedance of fast CMOS drivers, wherein the output impedance of a plurality of slaved drivers (DS1...DSn) is controlled by a circuit for measuring and correcting mismatch between one of the drivers (DM), taken as reference and dedicated to this aim, and the impedance at the input of a reference trans-mission line (L), equal to lines (L1...Ln) connected to the other drivers, the output impedance adjustment of the reference driver (DM) being carried out by a comparator comparing the maximum voltage of a clock signal supplied by that reference driver (DM) at the input of the reference line (L) with a reference voltage equal to half the supply voltage of the output stages of the drivers and dependant on the result of the comparison said comparator supplies a current which periodically charges or discharges a capacitor (C1), so as to obtain across its terminals a control voltage for the driver impedance, characterized in that a first clock signal is sent to the input (2, 3) of said reference driver (DM) producing a periodic signal on said reference line (L) terminated by a resistance (R) equal to its characteristic impedance and said periodic signal present at the reference line input is compared with said reference voltage in a threshold comparator (CO) in correspondence with the transitions of a second clock signal (on 6) with a frequency equal to that of the first clock signal, but in quadrature so as to carry out the comparison at the center of the half-period wherein the voltage at the input of the reference line (L) is maximum, the comparison result being used to charge or discharge the capacitor (C1), whose voltage is applied to the inputs of a plurality of buffer amplifiers, one (BU) of which controls the output impedance of the reference driver (DM) and the others (BU1...BUn) the output impedances of the slaved drivers (DS1...DSn).
Claim 3
Dependent Claim 36 words
An automatic system as in claim 1, characterized in that said clock signals present a frequency lower than the bit rate of data at the inputs of the slaved drivers (DS1...DSn), but an equal edge steepness.
Claim 4
Dependent Claim 37 words
An automatic system as in claim 1 or 2, characterized in that said clock signals present a frequency equal to about a fourth of the bitrate of the data at the inputs of the slaved drivers (DS1...DSn).
Claim 5
Dependent Claim 48 words
An automatic system as in any of claims 1 to 3, characte­rized in that the output voltage from said comparator (CO) is constant for the whole period of the second clock signal and that the comparison takes place after its outputs (7, 8) pass to high logic level.

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