Graphics processor having a floating point coprocessor

Claim 2

A graphics coprocessor comprising: transfer circuitry for transferring externally supplied and level instructions, and graphics data represetnative of points in a graphics display; processing circuitry having logic to provide multiple mathematical calculations to perform graphical functions with respect to the transferred graphics data in accordance with the end level instructions, the calculations having numerous intermediate steps, the results of the intermediate steps contained within said coprocessor; and circuitry for providing end results of the mathematical calculations externally.

Claim 3

The graphics coprocessor of claim 1 wherein said processing circuitry has a sequencer responsive to an end level instructions and a memory containing coded instructions retrievable by the sequencer in response to an end level instruction for controlling the steps of said processing unit.

Claim 4

The graphics coprocessor of claim 2 wherein said transfer circuitry includes registers and said processing circuitry includes calculation circuitry operable in response to the institution of a particular set of said coded instructions upon receipt of a single end level instruction for providing matrix calculations where certain intermediate results are stored in said registers while other intermediate results remain within said calculation circuitry available for subsequent use, thereby reducing storage requirements.

Claim 5

The graphics coprocessor of claim 1 wherein said processing circuitry includes an internal controller and circuitry operative jointly under control of externally provided instructions and said internal controller for enabling a particular instructional step for the performance of a selected mathematical operation on the data, and circuitry for directing said internal controller to operate either in a stand-alone mode under cotnrol of said internal controller or in conjunction with an external processor.

Claim 6

The graphics coprocessor of claim 1 wherein said processing circuitry includes circuitry and logic for computing, from a single externally provided instruction, a range of matrix and vector calculations suitable for constructing data point sets for controlling graphical presentations on a display medium.

Claim 7

The graphics coprocessor of claim 1 or 2 wherein said processing circuitry includes imaging calculation circuitry operable in response to the institution of a particular set of coded instructions upon transfer of a single end level isntruction for providing imaging calculations defining the viewable portion of a polygon given the vertices of said polygon.

Claim 8

The graphics processor of claim 1 or 2 wherein said processing circuitry includes imaging calculation circuitry for calculating the portion of a polygon within a viewing area.

Claim 9

The graphics coprocessor of claim 7 wherein said imaging calculation circuitry performs said viewing area determination by an examination of the polygon with respect to bounding planes defining the viewing area using pairs of the bounding planes.

Claim 10

The graphics coprocessor of claim 8 wherein said image calculation circuitry includes circuitry which calculates the position of the end points of a line segment to be contained within the viewing area or which cross the viewing area that lie on the lines defining the object under consideration, thereby relating to the bounding planes.

Claim 11

The graphics coprocessor of claim 1 or 2 wherein said processing circuitry includes image calculation circuitry for providing graphical calculations defining the viewable portion of an object within a viewing area given the vertices of the object, said circuitry operable for determining if the object is all within, partially within or totally outside said viewing area.

Claim 12

The graphics coprocessor of claim 10 wherein said image calculation circuitry is further operable for determining if the object is outisde on the same side of said viewing area or on opposite sides of said viewing area thus crossing the boundaries defining the viewing area.

Claim 13

The graphics coprocessor of claim 1 or 2 wherein said processing circuitry includes image calculation circuitry for determining the direction in which an object is facing with respect to a viewpoint.

Claim 14

The graphics coprocessor of claim 12 wherein aid image calculation circuitry includes circuitry for rejecting from further consideration those objects determined not to face the current viewpoint.

Claim 15

The graphics coprocessor of claim 1 or 2 wherein said processing circuitry includes image calculation circuitry for scaling to fit a specified biewpoing on the display surface of said object in accordance with data transferred thereto.

Claim 16

The graphics coprocessor of claim 1 or 2 wherein said processing circuitry includes image calculation circuitry for determining from a provided set of data representative of a line, the segment of the line falling within a certain viewing area.

Claim 17

The graphics coprocessor of claim 1 or 2 wherein said processing circuitry includes circuitry for providing vector calculations, including vector dd, vector subtract, vector scaling, dot product and vector product, all calculations based upon an initial set of data points transferred thereto by said transfer circuit.

Claim 18

The graphics coprocessor of claim 1, 2 or 16 wherein said processing circuitry includes circuitry for calculating light ray angles based upon vector mathematics.

Claim 19

The graphics coprocessor of claim 1, 2, 16 or 17 wherein said processing circuitry includes circuitry for determining from a provided set of data representative of a line where light rays will strike a surface.

Claim 20

A computer graphics system comprising: a host computer; a graphics processor connected to said host computer; and a graphics coprocesscr connected to said graphics processor and including: transfer circuitry for transferring from said graphics processor end level instructions and graphics data representative of points in a graphic display; processing circuitry having logic to provide multiple mathematical calculations to perform graphical functions with respect to the transferred graphics data in accordance with the end level instructions, the calculations having numerous intermediate steps, the results of the intermediate steps contained within said coprocessor; and circuitry for providing end results of the mathematical calculations to said graphics processor.

Claim 21

A computer graphics system comprising: a host computer; a graphics processor connected to said host computer; and a graphics coprocesscr connected to said graphics processor and including: transfer circuitry for transferring from said graphics processor end level instructions and graphics data representative of points in a graphic display; processing circuitry having logic to provide multiple mathematical calculations to perform graphical functions with respect to the transferred graphics data in accordance with the end level instructions, the calculations having numerous intermediate steps, the results of the intermediate steps contained within said coprocessor; and circuitry for providing end results of the mathematical calculations to said graphics processor.

Claim 24

A coprocessor comprising: a bus for communicating data to and from an external source; a plurality of registers for the acceptance of data from either an internal or an external source via said bus; a processing unit; a memory containing coded instructions for controlling the steps of said processing unit, said coded instructions operable for moving data in and out of said registers and to and from said bus during the performance of any of said coded instructions; and circuitry operable in response to the institution of a particular set of said coded instructions upon receipt of a single instruction via said bus for providing matrix calculations where certain intermediate results are stored in said registers while other intermediate results remain within said circuitry available for subsequent use, thereby reducing the number of storage registers required during any matrix arithmetic operation.

Claim 25

A coprocessor comprising: a bus for communicating data to and from an external source; a plurality of registers for the acceptance of data from either an internal or an external source via said bus; a processing unit; a memory containing coded instructions for controlling the steps of said processing unit, said coded instructions operable for moving data in and out of said registers and to and from said bus during the performance of any of said coded instructions; and circuitry operable in response to the institution of a particular set of said coded instructions upon receipt of a single instruction via said bus for providing matrix calculations where certain intermediate results are stored in said registers while other intermediate results remain within said circuitry available for subsequent use, thereby reducing the number of storage registers required during any matrix arithmetic operation.

Claim 26

A coprocessor comprising: a bus for communicating data to and from an external source; a plurality of registers for the acceptance of data from either an internal or an external source via said bus; a processing unit; a memory containing coded instructions for controlling the steps of said processing units said coded instructions operable for moving data in and out of said registers and to and from said bus during the performance of any of said coded instructions; and circuitry operable in response to the institution of a particular set of said coded instructions upon receipt of a single instruction via said bus for providing imaging calculations defining the viewable portion of a polygon given the vertices of said polygon.

Claim 27

A coprocessor comprising: a bus for communicating data to and from an external source; a plurality of registers for the acceptance of data from either an internal or an external source via said bus; a processing unit; a memory containing coded instructions for controlling the steps of said processing units said coded instructions operable for moving data in and out of said registers and to and from said bus during the performance of any of said coded instructions; and circuitry operable in response to the institution of a particular set of said coded instructions upon receipt of a single instruction via said bus for providing imaging calculations defining the viewable portion of a polygon given the vertices of said polygon.

Claim 28

A coprocessor comprising: a bus for communicating data to and from an external source; a plurality of registers for the acceptance of data from either an internal or an external source via said bus; a processing unit; a memory containing coded instructions for controlling the steps of said processing unit, said coded instructions operable for moving data in and out of said registers and to and from said bus during the performance of any of said coded instructions; and circuitry operable in response to the institution of a particular set of said coded instructions upon receipt of a single instruction via said bus for providing graphical calculations defining the viewable portion of an object given the vertices of the object, said circuitry operable for determining if the object is all within, partially within or totally outside said viewing area, said circuitry further operable for determining if said object is outside on the same side of said viewing area or on opposite sides of said viewing area thus crossing the boundaries defining the viewing area.

Claim 29

A coprocessor comprising: a bus for communicating data to and from an external source; a plurality of registers for the acceptance of data from either an internal or an external source via said bus; a processing unit; a memory containing coded instructions for controlling the steps of said processing unit, said coded instructions operable for moving data in and out of said registers and to and from said bus during the performance of any of said coded instructions; and circuitry operable in response to the institution of a particular set of said coded instructions upon receipt of a single instruction via said bus for providing graphical calculations defining the viewable portion of an object given the vertices of the object, said circuitry operable for determining if the object is all within, partially within or totally outside said viewing area, said circuitry further operable for determining if said object is outside on the same side of said viewing area or on opposite sides of said viewing area thus crossing the boundaries defining the viewing area.

Claim 30

The coprocessor set forth in Claim 1, wherein said last-mentioned circuitry is further operative in response to said institution of a particular set of said coded instructions for performing a matrix multiplication on up to 4X4 matrices using only 20 registers for storing said intermediate results.