Semiconductor integrated circuit including an intrinsic MOS transistor for generating a reference voltage

Claim 2

A semiconductor integrated circuit according to claim 1, wherein said means for connecting the drain(9) to the gate (12) comprises wiring. 12. A semiconductor integrated circuit for generating a reference voltage, comprising: a semiconductor substrate(14) having a first conductivity type; a first voltage terminal connected to a first voltage source; a load element(5) formed in the semiconductor substrate (10) and having two ends, one end of which is connected to the first voltage terminal; a second voltage terminal connected to second voltage source; and a well impurity region(15) of the second conductivity type formed in the substrate; characterized by an intrinsic MOS transistor(6) formed in the well impurity region(15) and having a channel(18) with an impurity concentration substantially the same as that of an upper portion of the well impurity region-(15), a source(16), a drain (17) and a gate(20); means for connecting the other end of the load element(5) to the source(16); means for connecting the second voltage terminal to the drain(17); means for connecting the drain(17) to the gate(20); and an output terminal(7) connected to the other end of the load element(5) and to the source(16).

Claim 3

A semiconductor integrated circuit for generating a reference voltage, comprising: a semiconductor substrate(21) having a first conductivity type; a first voltage terminal connected to a first voltage source; a load element(5) formed in the semiconductor substrate(21) and having two ends, one end of which is connected to the first voltage terminal; a second voltage terminal connected to second voltage source; a first well impurity region(22) of a second conductivity type formed in the substrate(21); and a second well impurity region(23) of the first conductivity type formed in the first well impurity region(22); characterized by an intrinsic MOS transistor(6) formed in the second well impurity region(23), having a channel(26) with an impurity concentration substantially the same as that of an upper portion of the second well impurity region(23), a source (24), a drain(25) and a gate-(28); means for connecting the other end of the load element to the source(24); means for connecting the second voltage terminal to the drain(25); means for connecting the drain(25) to the gate(28); and an output terminai(7) connected to the other end of the load element(5) and to the source(24). 14. A semiconductor integrated circuit for generating an internal power source voltage comprising: a semiconductor substrate(10); a first voltage terminal connected to a first voltage source; a load element(5) formed in the semiconductor substrate(10) and having two ends, one end of which is connected to the first voltage terminal; and a second voltage terminal connected to a second voltage source; characterized by an intrinsic MOS transistor (6) formed in the semiconductor substrate(10) and having a source(8), a drain(9) and a gate(12) and a channel (13) having no channel ion-implantation for threshold control; means for connecting the other end of the load element(5) to the source(8); means for connecting the second voltage terminal to the drain(9); means for connecting the drain(9) to the gate(12); an output terminal (7) connected to the other end of the load element(5) and to the source(8); and a power source voltage generating circuit (36) formed in the semiconductor substrate(10) and having a reference voltage level input terminal connected to the output terminal(7); at least one MOS transistor which is formed with channel ion-implantation, and an internal power source voltage between the voltage level of the output terminal and the voltage level of the second voltage terminal. 15. A semiconductor integrated circuit according to claim 14, wherein the power source voltage generating circuit (36) comprises: a first P-channel MOS transistor(37) having a source connected to the first voltage terminal, a drain and a gate; a second P-channel MOS transistor(38) having a source connected to the first voltage terminal, a drain connected to the gate of the first P-channel MOS transistor(37), and a gate; a third P-channel MOS transistor(39) having a source connected to the first voltage level, a gate connected to the gate of the second P-channel MOS transistor(38) and a drain connected to the gate of the third P-channel transistor(39); a first N-channel MOS transistor (40) having a drain connected to the gate of the first P-channel MOS transistor(37) and the drain of the second P-channel MOS transistor(38), a gate connected to the reference voltage level input terminal, and a source; a second N-channel MOS transistor (41) having a drain connected to the gate of the second P-channel MOS transistor(38) and the gate and the drain of the third P-channel MOS transistor(39), a source connected to the source of the first N-channel MOS transistor(40), and a gate; a third N-channel MOS transistor (42) having a drain connected to the source of the first N-channel MOS transistor(40) and the source of the second N-channel MOS transistor(41), a gate connected to the gate of the second MOS transistor(41), and a source connected to the second voltage terminal; a first load element (44) connected between the drain of the first P-channel MOS transistor and the gate of the second N-channel MOS transistor; a second load element(45) connected between the gate of the second N-channel MOS transistor (41) and the second voltage terminal; and a connecting terminal (46) connected between the drain of the first P-channel MOS transistor and the first load element. 16. A semiconductor integrated circuit according to claim 14, wherein the first load element (44) is a resistor and the second load element(45) is a resistor. 17. A semiconductor integrated circuit for generating comparing signal comprising: a semiconductor substrate(10); a first voltage terminal connected to a first voltage source; a load element(5) formed in the semiconductor substrate and having two ends, one end of which is connected to the first voltage terminal; and a second voltage terminal connected to a second voltage source; characterized by an intrinsic MOS transistor (6) formed in the semiconductor substrace and having a source(8), a drain(9), a gate(12) and a channel (13) having no ion-implantation for threshold control; means for connecting the other end of the load element(5) to the source(8); means for connecting the second voltage terminal to the drain(9); means for connecting the drain(9) to the gate(12); an output terminal(7) connected to the other end of the load element(5) and to the source(8); and a comparing circuit(47) formed in the semiconductor substrate(10) for comparing a value of an external input signal(59) with a value of a reference voltage produced at the output terminal (7) and having at least one MOS transistor which is formed with channel ion-implantation.