An information processing device having an error check and correction circuit

Assignee: NEC Corp

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Filing: 1991-02-26

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Granted: —

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Expires: 2011-02-26

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Abstract

Abstract An information processing device according to the present invention includes a logical circuit which outputs a signal (S11;S30) for indicating that an error correction has been conducted on a data, when an error check and correction (ECC) circuit detects and corrects an error of data at the time of reading data from a memory cell array (2;21,22) of an electrically erasable programmable ROM (EEPROM). In the information processing device of the present invention, while the EEPROM outputs the correct data by means of the ECC circuit, it can be known whether there exists an error even in a part of the cells in the EEPROM, so that it is possible to alter an address of a memory cell containing an erroneous bit in the EEPROM or to change the EEPROM itself before malfunction occurs in the information processing device having the EEPROM due to a breakdown of the memory cells in the EEPROM.

Inventors

👤 Toshihide C/O Nec Corporation Tsuboi

Bibliographic Details

Application Number —

Jurisdiction EP

Data Source google_patents

Last Synchronized 2026-10-29 09:13

CPC Classifications

G; G11; G11C; G11C29/00; G11C29/70; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1076

Claims Analysis

Total Claims: 5

Claim 1

Independent Claim 76 words

An information processing device having an array of EEPROM cells (2;21,22) and an error check and correction circuit which checks and corrects an error in bits forming a data read out from said array of EEPROM cells, characterized in that said information processing device includes a logical circuit which outputs a signal (S11;S30) for indicating the execution of an error correction when said error check and correction circuit detects and corrects said error in said bits.

Claim 2

Dependent Claim 89 words

An information processing device according to claim 1, wherein said error check and correction circuit is characterized by having:- a syndrome generating circuit (5) which generates a syndrome signal (S6) on the basis of said data (4,14) inputted to said syndrome generating circuit; an error vector generating circuit (7) which decodes said syndrome signal (S6) and generates an error vector signal (S8) for showing which bit in said data is an error bit; and an error correction circuit (9) which corrects the detected error and outputs a corrected data.

Claim 3

Dependent Claim 176 words

An information processing device characterized by comprising:- an array of EEPROM cells (2); a selector (3) which selects a cell corresponding to an address to be read out from said array of EEPROM cells (2) and outputs main data (14) and redundant data (4), said main data having the same number of bits as an original data; a syndrome generating circuit (5) which generates a syndrome signal (S6) on the basis of said main data (14) and redundant data (4) inputted to said syndrome generating circuit (5); an error vector generating circuit (7) which decodes said syndrome signal (S6) and generates an error vector signal (S8) for showing which bit in said main data and redundant data is an error bit; an error correction circuit (9) which corrects the detected error and outputs a corrected data; and a logical sum circuit (1) which receives said syndrome signal (S6) and outputs a signal (S11) for indicating the execution of an error correction when said error check and correction circuit detects and corrects said error in said bits.

Claim 4

Dependent Claim 103 words

An information processing device characterized by comprising:- an array of EEPROM cells (21,22); an error check and correction circuit which checks and corrects an error in bits forming a data read out from said array of EEPROM cells; a logical circuit which outputs a signal (S30) for indicating the execution of an error correction when said error check and correction circuit detects and corrects said error in said bits; and an address altering means (25,28) which alters an address storing said data in said array of EEPROM cells on the basis of said signal (S30) for indicating the execution of the error correction.

Claim 5

Dependent Claim 69 words

An information processing device according to claim 4, wherein said address altering means includes a latch (28) which is set on the basis of said signal (S30) for indicating the execution of the error correction and an adder (25) which adds a predetermined value to the value of said address and outputs the value thus added up as a value of new address when said latch (28) is set.

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