EP0450632A2
Expired / Lapsed
EP
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Nonvolatile semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1991-04-05
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Granted: —
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Expires: 2011-04-05
Abstract
Abstract A decoder (32) contains AND gates (42₀, 42₁, ...), which each receive a unique combination of internal address signals (a0 through a12, a0 through a12 ) consisting of a plurality of bits, and OR gates (41₀, 41₁, ...), which each receive the output of the AND gates (42₀, 42₁, ...) respectively and each also receive two types of control signals (CH0, CH1) alternately. During test, one of the two types of control signals (CH0, CH1) is activated depending on the logic level of the odd/even signal (ODD/ EVEN ) supplied to the control circuit (36) which enables simultaneous selection of the word lines previously given the either even or odd addresses from the word lines (WL0, WL1, ...) connected to the memory cell array (33), on the basis of the output of the decoder (32).
Inventors
- 👤 Hitoshi Intellectual Property Division Kondo
- 👤 Satoshi Intellectual Property Division Sasaki
- 👤 Tadashi Intellectual Property Division Maruyama
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 00:35
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/10; G11C16/00; G11C16/02; G11C16/06; G11C16/08; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/30; G11C29/34; G11C8/12
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
105 words
A nonvolatile semiconductor memory device, comprising: a memory cell array (33) containing a plurality of words of nonvolatile memory elements; a plurality of word lines (WL0 through WL8191) each of which is connected to one word of nonvolatile memory elements in said memory cell array and is given a particular address in said memory cell array; and selecting means (31, 32, 36; 31, 32, 38) which divides the word lines into a plurality of groups depending on the addresses each given to the word lines and which simultaneously selects the word lines belonging to one of the groups according to the control signal during test.
Claim 2
Dependent Claim
36 words
A nonvolatile semiconductor memory device according to claim 1, characterized in that said selecting means selects either the even-address group of word lines or the odd-address group of word lines simultaneously, depending on said control signal.
Claim 3
Dependent Claim
141 words
A nonvolatile semiconductor memory device according to claim 2, characterized in that said selecting means includes: an address buffer (31) which receives an external address signal consisting of a plurality of bits to select said word lines and produces an internal address signal based on the external address signal; a control circuit (36, 38) which receives a first control signal (ODD/ EVEN ) to distinguish between the even-address group of word lines and the odd-address group of word lines and which produces a second and third control signals (CH0, CH1) based on the logic level of the first control signal; and a decoder (32) which receives said internal address signal of a plurality of bits and said second and third internal control signals, and which selects the word lines based on those internal address signal and second and third control signals.
Claim 4
Dependent Claim
104 words
A nonvolatile semiconductor memory device according to claim 3, characterized in that said control circuit further receives a fourth control signal (TEST) to select either the normal data read/write operation or the test operation for said memory cell array and includes: an inverter circuit (46) which inverts the logic level of said first control signal; a first AND gate circuit (43) which receives said fourth control signal and the output of said inverter circuit and produces said second control signal; and a second AND gate circuit (44) which receives said fourth control signal and said first control signal and produces said third control signal.
Claim 5
Dependent Claim
90 words
A nonvolatile semiconductor memory device according to claim 4, characterized in that said decoder includes: a plurality of third AND gate circuits (42) which each provide for said corresponding word lines and each receive said internal address signal con sisting of a plurality of bits (a0 through a12, a0 through a12 ); and a plurality of first OR gate circuits (41) which each provide for said corresponding word lines and each receive the output of said corresponding third AND gate circuits and one of said second and third control signals.
Claim 6
Dependent Claim
163 words
A nonvolatile semiconductor memory device according to claim 3, characterized in that said control circuit further receives a fourth control signal (TEST) to select either the normal data read/write operation or said memory-cell array test operation and a fifth control signal (TMODE) to select either said endurance test or said retention test of said memory cell array, and includes: an inverter circuit (46) which inverts the logic level of said first control circuit; a second OR gate (45) which receives said fifth control signal and the output of said inverter circuit; a third OR gate circuit (47) which receives said fifth control signal and said first control signal; a fourth AND gate circuit (43) which receives said fourth control signal and the output of said second logical-sum gate circuit and produces said second control circuit; and a second OR gate circuit (44) which receives said fourth control signal and the output of said second logical-sum gate circuit and produces said third control signal.
Claim 7
Dependent Claim
38 words
A nonvolatile semiconductor memory device according to claim 1, characterized by further comprising data generating means (51₁ through 51₄) for generating data consisting of a plurality of bits to be written into said memory cell array during test.
Claim 8
Dependent Claim
102 words
A nonvolatile semiconductor memory device according to claim 2, characterized by further comprising data generating means (51₁ through 51₄) for generating data consisting of a plurality of bits to be written into said memory cell array during test, wherein said data generating means generates data of an alternate logical 1 and 0 string when one of the even-address group and the odd-address group of the word lines is selected by said selecting means, while it generates data of an alternate logical 0 and 1 string when the other of the even-address group and the odd-address group of the word lines is selected.
References Cited (Backward Citations)
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