EP0453171A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Method for substantially eliminating hold time violations in implementing high speed logic circuits or the like
Assignee: Quickturn Design Systems Inc
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Filing: 1991-04-10
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Granted: —
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Expires: 2011-04-10
Abstract
Abstract A method is provided for automatically ensuring synchronized operation of a sequential logic circuit which is implemented from a user net list containing the logic configuration data of a prototype circuit. The method includes providing a synchronizer flip-flop device or latch corresponding to every flip-flop device or latch in the user's original net list. The synchronizer flip-flop is connected to its corresponding original user flip-flop immediately upstream in the data path to the original flip-flop device. A predetermined amount of delay is added to the user's original clock and data signals. For each master clock in the user net list, a synchronizing clock signal generator derives a synchronizer clock which is delayed relative to the user's original clock. The synchronizing clock is applied to each control lead of each synchronizer flip-flop. The synchronizing clock always arrives at the synchronizer flip-flops before the user's clock and before the user's data. Moreover, it does not matter in what order the data and user's clock arrives. The method provides synchronized operation and eliminates hold time violations in implementing a circuit from a user net list, even in the presence of clock skew.
Inventors
- 👤 Roderick A. Price
- 👤 Bart C. Thielges
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 14:24
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4208; G06F13/4217; G06F30/00; G06F30/30; G06F30/32; G06F30/327; G06F30/33; G06F30/3308; G06F30/3312
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
200 words
A method for providing synchronized operation of a sequential logic circuit being implemented from a net list or logic configuration data, or the like including a plurality of clocked flip-flop devices controlled from one or more clock signals generated from at least one common frame of reference, each of said flip-flop devices having a data input lead for receiving data signals, a clock input for receiving said clock signals and an output comprising the steps of: providing upstream in the data path with respect to each original flip-flop device in said net list, a corresponding synchronizer flip-flop device having a data input connected for receiving a data signal, an output connected to the data input of each corresponding flip-flop device, and a control clock input, delaying said clock signals applied to the clock input of each of said original flip-flop devices, generating, from each original clock signal on the same frame of reference, a synchronizing clock and applying said generated synchronizing clock to the clock inputs of each of said synchronizer flip-flop devices, allowing said clock and data signals to propagate through said synchronizing flip-flop devices and said original flip-flop devices to provide a synchronized configuration of said implemented circuit.
Claim 2
Dependent Claim
79 words
The method of claim 1 wherein the step of determining the amount of delay to be added to said clock signals includes the step of first determining the amount of clock skew in the logic circuit described by the net list and adding enough delay on the clock input leads such that said clock signal always arrives at the control input of said original flip-flop after the synchronizing clock signal arrives at the control input of said synchronizer flip-flop.
Claim 3
Dependent Claim
76 words
The method of claim 1 wherein said step of deriving a synchronizing clock from each original clock on the same frame of reference includes the step of gating said original clock signal and said delayed clock signal through an Exclusive - OR gate such that said gated clock signals appear at the clock input of each of said synchronizer flip-flop devices before any original clock signal appears at said clock input of said original flip-flop device.
Claim 4
Independent Claim
208 words
A method for providing synchronized operation of a digital logic circuit or the like being implemented from a user net list describing logic circuit configuration data including a plurality of clocked transparent latches controlled from one or more user clock signals of a clock net generated from at least one common frame of reference, each of said transparent latches having a data input for receiving data signals, a clock input for receiving said clock signals and an output comprising the steps of: providing upstream in the data path with respect to each user transparent latch device in said user net list, a corresponding synchronizer latch having a data input connected for receiving a data signal, an output connected to the data input lead of each corresponding user transparent latch, and a clock input, delaying said clock signals applied to the clock inputs of each of said user's transparent latches, generating, from each user original clock signal on the same frame of reference, a synchronizing clock and applying said generated synchronizing clock to the clock inputs of each of said synchronizer latches, allowing said clock and data signals to propagate through said synchronizer latches and said user transparent latches to provide a synchronized configuration of said user net list.
Claim 5
Dependent Claim
80 words
The method of claim 4 wherein the step of determining the amount of delay to be added to said clock signals includes the step of first determining the amount of clock skew in the logic circuit described by the user net list and adding enough delay on the clock inputs such that the clock signal always arrives at the control input of said user original latch after said synchronizing clock signal arrives at said control input of said synchronizer latch.
Claim 6
Dependent Claim
78 words
The method of claim 4 wherein said step of deriving a synchronizing clock from each user original clock on the same frame of reference includes the step of gating said original clock signal and said delayed clock signal through an Exclusive - OR gate such that said gated clock signals appear at said clock input of each of said synchronizer latch devices before any original user clock signal appears at said clock input of said original transparent latch.
Claim 7
Dependent Claim
75 words
The method of claim 4 wherein the width of the synchronizing clock is adjusted by first determining the amount of skew in the synchronizing clock net and in the user clock net, then setting the width of the synchronizing clock such that the falling edge at the synchronizing latch occurs after the rising or falling edge of the user clock at the corresponding original user latch for all latches in the original user net list.
References Cited (Backward Citations)
No citation records indexed.
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