EP0458385A2
Expired / Lapsed
EP
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Wholly digital process for the generation of multi-level modulation signals
Assignee: Italtel SpA
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Filing: 1991-05-10
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Granted: —
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Expires: 2011-05-10
Abstract
Abstract A process for actuation of multi-level digital modulation and in particular QAM modulation by using a single microprocessor (DSP) is described. The process calls for synchronism of all the frequencies in play and comprises an oversampling of the symbols of the 'in phase' and 'in quadrature' channels and appropriate digital filtration thereof. A digital carrier is QAM modulated simply by selecting in string the symbols belonging to said digitally filtered channels taken with their true of negated value. Said symbols are then sent to a digital/analog converter (DAC) followed by a reconstruction filter (FRIC) to obtain the corresponding QAM modulated analog carrier. <IMAGE>
Inventors
- 👤 Michelangelo Lo Curto
- 👤 Marcello Salerno
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 10:21
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/32; H04L27/34; H04L27/36; H04L27/365
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
261 words
Multi-level digital modulation process wherein a serial flow (S in ) having a bit frequency fb is parallelized forming first words of N bits called symbols (SIMB) having a symbol frequency fs from which are generated in synchronism second (Ii) and third words (Qi) belonging to a channel termed 'in phase' and a channel termed 'in quadrature' respectively, components along two orthogonal axes of a vector which digitally modulates a sinusoidal carrier both in phase and in amplitude (Vo(t)), characterized in that: said second and third words (Ii,Qi) having a symbol frequency fs are filtered digitally at a sampling frequency fc synchronous with said symbol frequency fs and corresponding to said symbol frequency fs multiplied by an appropriate number K greater than two; said sinusoidal carrier modulated digitally both in phase and amplitude (Vo(t)) has a frequency (fo) synchronous with said sampling frequency fc and equal to one fourth of said sampling frequency fc; said digital filtration comprises cycles divided in four time intervals corresponding to an equal number of consecutive periods of said sampling frequency fc, there being generated in an orderly manner in said cycles fourth (Io), fifth (Qo), sixth ( I o) and seventh ( Q o) words corresponding to said second ( I i) and third ( Q i) true filtered words and to said second (Ii) and third (Qi) negated filtered words respectively, considered in the associated time interval, and that said fourth (Io), fifth (Qo), sixth ( I o) and seventh ( Q o) words constitute discrete samples of said digitally modulated sinusoidal carrier (Vo(t)).
Claim 2
Dependent Claim
236 words
Multi-level digital modulation process in accordance with claim 1 characterized in that said digital filtration of said second and third words is of the transverse type with finite pulse response and consists: in a first of said four time intervals, of the multiplication of a first array (BUFFERCOEFF) comprising a number p of digital coefficients (C1 ... Cp), for a second sequence (BUFFERIN.I) comprising a number M of said second words (Ii) and the summation of all the products obtaining in correspondence said fourth words (Io); in a second of said four time intervals, of the multiplication of said first array (BUFFERCOEFF) for a third sequence (BUFFERIN.Q) comprising said number M of said third words (Qi) and summation of all the products obtaining in correspondence said fifth words (Qo); in a third of said four time intervals, of the multiplication of said first array (BUFFERCOEFF) by said second sequence (BUFFERIN.I), summation of all the products and negation of the result obtaining in correspondence said sixth words ( I o); in a fourth of said four time intervals, of multiplication of said first sequence (BUFFERCOEFF) by said third sequence (BUFFERIN.Q), summation of all the products and negation of the result obtaining in correspondence said seventh words ( Q o); said number of digital coefficients p being equal to the product of said number M of words belonging to said second or third sequence by said number K.
Claim 3
Dependent Claim
145 words
Multi-level digital modulation process in accordance with claim 2 characterized in that said multiplications of said first array (BUFFERCOEFF) by said second (BUFFERIN.I) and third (BUFFERIN.Q) sequences comprise M products of each of the words contained in the respective sequences multiplied by a corresponding coefficient (C1 ... C p ) belonging to said first array (BUFFERCOEFF), each word belonging to said second and third sequences being identified by values taken from a first index d varying from 1 to M by unitary increments in a given period of said frequency fc, and each said corresponding coefficient (C1 ... Cp) being identified by values taken from a second index y dependent on said first index d, on said number K and on the value of a third NCAMP index varying from zero to K by increments of one unit at each period of said frequency fc.
Claim 4
Dependent Claim
28 words
Multi-level digital modulation process in accordance with claim 3 characterized in that said index y has the following expression: y = K x (d-1) + NCAMP + 1
Claim 5
Dependent Claim
40 words
Multi-level digital modulation process in accordance with claim 2 characterized in that at each period of said symbol frequency (fs) all the words belonging to said second (BUFFERIN.I) and third (BUFFERIN.Q) sequences undergo a shift of one position without recovery.
Claim 6
Dependent Claim
35 words
Device for actuation of Multi-level digital modulation in accordance with the process of claim 1 characterized in that it is embodied by means of a single microprocessor designed for processing digital signals in real time.
Claim 7
Dependent Claim
129 words
Device for actuation of multi-level digital modulation in accordance with the process of claim 6 characterized in that it also comprises: an oscillator circuit for the generation of a clock signal for timing the operation of said microprocessor, a synchronization circuit for generation of one or more timing signals sent to said microprocessor for timing the input and parallelization phases of said serial flow (Sin) and the digital filtration and modulation phases, a digital/analog converter (DAC) for conversion from digital to analog of said fourth (Io), fifth (Qo), sixth ( I o) and seventh ( Q o) words obtaining an equal number of discrete samples of said digitally modulated sinusoidal carrier (Vo(t)), and a low-pass filter (FRIC) for filtering said discrete samples reconstructing said digitally modulated sinusoidal carrier (Sout).
References Cited (Backward Citations)
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