EP0459232A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Partially decoded instruction cache

Assignee: National Semiconductor Corp

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Filing: 1991-05-16

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Granted: —

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Expires: 2011-05-16

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Abstract

Abstract A microprocessor partially decodes instructions retrieved from main memory before placing them into the microprocessor's integrated instruction cache. Each storage location in the instruction cache includes two slots for decoded instructions. One slot controls one of the microprocessor's integer pipelines and a port to the microprocessor's data cache. A second slot controls the second integer pipeline or one of the microprocessor's floating point units. The instructions retrieved from main memory are decoded by a loader unit which decodes the instructions from the compact form as stored in main memory and places them into the two slots of the instruction cache entry according to their functions. In addition, auxiliary information is placed in the cache entry along with the instruction to control parallel execution as well as emulation of complex instructions. A bit in each instruction cache entry indicates whether the instructions in the two slots are independent, so that they can be executed in parallel, or dependent, so that they must be executed sequentially. Using a single bit for this purpose allows two dependent instructions to be stored in the slots of the single cache entry.

Inventors

👤 Donald B. Alpert
👤 Dror Avnon
👤 Amos Ben-Meir
👤 Ran Talmudi

Bibliographic Details

Application Number —

Jurisdiction EP

Data Source google_patents

Last Synchronized 2026-10-24 10:59

CPC Classifications

G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3818; G06F9/382; G06F9/3017; G06F9/30174; G06F9/3802; G06F9/3822; G06F9/3836; G06F9/3853; G06F9/3877; G06F9/3885

Claims Analysis

Total Claims: 6

Claim 1

Independent Claim 76 words

A processor that executes instructions retrieved from a main memory external to the processor from an internal instruction cache memory, the processor comprising: (a) means for retrieving an encoded instruction from the main memory; (b) means for decoding the encoded instruction retrieved from main memory; (c) internal cache memory storage means for storing the decoded instruction; and (d) means for retrieving the decoded instruction from the internal cache memory storage means for execution by the processor.

Claim 2

Dependent Claim 117 words

A microprocessor that executes instructions retrieved from a main memory external to the microprocessor or from an internal instruction cache memory, the microprocessor comprising: (a) a plurality of functional units for executing instructions; (b) means for retrieving encoded instructions from main memory; (c) means for decoding the encoded instructions retrieved from main memory; (d) internal cache memory storage means comprising a plurality of storage locations, each storage location comprising a plurality of storage slots, each of the storage slots comprising means for storing a decoded instruction; and (e) means for simultaneously retrieving a plurality of decoded instructions from the storage slots of a selected cache memory storage location for parallel execution by the plurality of functional units.

Claim 3

Dependent Claim 57 words

A microprocessor as in claim 2 wherein each of the cache memory storage locations includes means for storing auxiliary information indicative of whether the plurality of instructions stored in the slots a cache memory storage location are independent such that the instructions may be executed in parallel, or dependent such that the instructions must be executed sequentially.

Claim 4

Independent Claim 73 words

A method of executing instructions by a processor that retrieves instructions from a main memory external to the processor or from an internal instruction cache memory, the method comprising: (a) retrieving an encoded instruction from the main memory; (b) decoding the encoded instruction retrieved from main memory; (c) storing the decoded instruction in an internal cache memory; and (d) retrieving the decoded instruction from the internal cache memory for execution by the processor.

Claim 5

Independent Claim 123 words

A method of executing instructions by a microprocessor that retrieves instructions from a main memory external to the microprocessor or from an internal instruction cache memory, the microprocessor including a plurality of functional units for executing instruction, the method comprising: (a) retrieving encoded instructions from main memory; (b) decoding the instructions retrieved from main memory; (c) storing the decoded instructions in an internal cache memory storage means comprising a plurality of storage locations, each storage location comprising a plurality of storage slots, each of the storage slots comprising means for storing a decoded instruction; and (d) simultaneously retrieving a plurality of decoded instructions from the storage slots of a selected cache memory storage locatio for parallel execution by the plurality of functional units.

Claim 6

Dependent Claim 62 words

A method as in claim 5 and including the step of storing auxiliary information in the cache memory storage locations, the auxiliary information being indicative of whether the plurality of instructions stored in the slots of a cache memory storage location are independent such that the instructions may be executed in parallel, or dependent such that the instructions must be executed sequentially.

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