D.C. offset compensation in a radio receiver

Claim 2

The apparatus defined in claim 1, further comprising: an estimating means, connected to said restoring means, for estimating an error in the DC component; memory means, connected to said restoring means, for storing the restored signal; and subtracting means for subtracting the estimated error component from the restored signal stored in said memory means to thereby substantially free the signal output from said subtracting means from low frequency distortion.

Claim 3

The apparatus as defined in claim 2, wherein said estimating means includes a digital signal processor which determines the estimated DC component based on a pattern deliberately inserted in the channel signal.

Claim 4

The apparatus as defined in claim 2, wherein said estimating means includes a digital signal processor which determines the estimated DC component based on an inherent waveform characteristic of the channel signal.

Claim 5

The apparatus as defined in claim 1, wherein said blocking means includes a delta modulator to block DC signal components and digitize the received channel signal.

Claim 7

The apparatus defined in claim 6, further comprising: an estimating means, connected to said integrating means, for estimating the value of the recovered DC component; memory means, connected to said integrating means, for storing a restored signal output from said integrating means, wherein the restored signal includes the amplified signal and the recovered DC component; and subtracting means for subtracting the estimated DC component value from the restored signal stored in said memory means, whereby the signal output from said subtracting means is substantially free from low frequency distortion.

Claim 8

The apparatus as defined in claim 6, wherein both said differentiating and integrating means consist of a single capacitor.

Claim 9

The apparatus as defined in claim 6, further comprising: an analog-to-digital converter for converting the output from said amplifying means to digital signals, and said integrating means includes means for numerically integrating the digital signals output from said analog-to-digital converter.

Claim 10

The apparatus as defined in claim 9, wherein said differentiating means and said analog-to-digital converter include a delta modulator.

Claim 11

The apparatus as defined in claim 7, wherein said estimating means includes a digital signal processor which determines the restored DC component based on a pattern deliberately inserted in the channel signal.

Claim 12

The apparatus as defined in claim 7, wherein said estimating means includes a digital signal processor which determines the restored DC component based on an inherent characteristic of the channel signal.

Claim 13

A radio receiving apparatus for receiving an RF signal and applying said RF signal to first and second quadrature channels, comprising: a local oscillator; first and second mixers, associated with said first and second quadrature channels, respectively, each having one input for receiving said RF signal and a second input for receiving from said oscillator sinusoidal signals at the carrier frequency of said RF signal; first and second differentiating means for respectively differentiating the outputs from said first and second mixers in order to eliminate DC offset voltages generated by imbalances between said first and second mixers; first and second amplifying means for respectively amplifying the outputs from said first and second differentiating means; and first and second integrating means for respectively integrating the outputs from said first and second amplifying means to restore DC components of said RF signal.

Claim 14

The apparatus as defined in claim 13, further comprising: estimating means, connected to said first and second integrating means, for estimating errors in said restored DC offset components; memory means, connected to said first and second integrating means, for storing signals output from said first and second integrating means; and combining means for combining said estimated components with said stored signals to thereby substantially free the output of the combining means from low frequency distortion.

Claim 15

The apparatus as defined in claim 13, wherein said first and second differentiating means and said first and second integrating means each respectively consist of a single capacitor.

Claim 16

The apparatus as defined in claim 13, wherein said first and second differentiating means include a delta modulator technique to differentiate the outputs of said first and second mixers and to digitize the differentiated outputs.

Claim 17

The apparatus as defined in claim 16, wherein said first and second integrating means include a digital signal processor programmed to numerically integrate the output from said first and second amplifiers.

Claim 18

The apparatus as defined in claim 14, wherein said estimating means includes a digital signal processor which determines said DC error components based on a deliberately inserted pattern in the received RF signal.

Claim 19

The apparatus as defined in claim 14, wherein said estimating means includes a digital signal processor which determines said DC offset components based on an inherent characteristic of said received RF signal.

Claim 21

The apparatus according to claim 20, wherein said digital values represent the digitized derivative of said received signal.

Claim 22

The apparatus according to claim 20, wherein said second integrating means includes an up/down counter means for counting up when a first digital signal is received and down when a second digital signal is received.

Claim 23

The apparatus according to claim 20, wherein said current step values are positive and negative step values based on said sequence of digital values.

Claim 24

The apparatus according to claim 23, wherein said deciding means increases and decreases the magnitude of said positive and negative step values based on patterns in said sequence.

Claim 25

A radio receiving apparatus for receiving an RF signal and applying said RF signal to first and second quadrature channels, comprising: means for receiving said RF signal and separating said RF signal into first and second quadrature signals; a local oscillator; first and second comparator means for comparing said first and second quadrature signals with first and second feedback signals respectively, and for outputting a first digital value if said received signal exceeds said feedback signal and a second digital value if said received signal is less than said feedback signal; first and second memory means for storing corresponding sequences of said digital values output from said first and second comparator means, respectively; deciding means, connected to said first and second latch means, for receiving said sequences of digital values and for deciding a joint current step value; first and second integrating means for integrating joint current step values received from said deciding means and for outputting said first and second feedback signals to said first and second comparator means, respectively; and first and second reintegrating means for reintegrating said corresponding digital values in order to restore DC offset components of said channel signal.

Claim 26

A radio receiver for receiving an RF signal and applying said RF signal to plural channels, comprising: means for receiving said RF signal and separating said RF signals into a plurality of mixers; plural delta modulating means for receiving respective outputs from corresponding plural mixers, each delta modulating means generating a digital output; plural memory means for storing digital sequences of digital outputs from corresponding ones of said plural delta modulating means; adaptive means, connected to said plural memory means, for adapting step value signals fed back to corresponding ones of said plural delta modulating means; and plural reintegrating means for integrating a corresponding digital output in order to restore DC components of said RF signal.

Claim 27

The apparatus according to claim 26, wherein said step value signals are identical for each delta modulating means and any adaptation by said adaptive means is uniformly applied to said step value signals.

Claim 28

The apparatus according to claim 26, wherein each of said plural delta modulating means includes: comparator means for comparing a respective mixer output with a feedback RF signal and for outputting a first digital value if said RF received signal exceeds said feedback signal and a second digital signal value if said received RF signal is less than said feedback signal; clock means for generating a clock pulse; latch means, connected to said clock means, for latching a sequence of digital values output from said comparator means at each clock pulse; deciding means, connected to said latch means, for receiving said sequence of digital values and for deciding a current step value; integrator means for integrating current step values received from said deciding means and for outputting said feedback signal to said comparator means.

Claim 29

A radio receiver as defined in claim 26, further comprising: plural estimating means, connected to said plural reintegrating means, for estimating errors in the restored DC offset components; plural memory means, connected to said plural reintegrating means, respectively, for storing signals output from said plural reintegrating means; and plural combining means for algebraically combining said estimated DC offset error components with said stored signals to thereby substantially free the output of each combining means from low frequency distortion.

Claim 30

The apparatus as defined in claim 29, wherein said plural estimating means include processing means for determining said DC error components based on a deliberately inserted pattern in said received RF signal.

Claim 31

The apparatus as defined in claim 29, wherein said estimating means include processing means which determine said DC error components based on an inherent characteristic of said received RF signal.

Claim 33

The method according to claim 29, further comprising: increasing the magnitude of said current step value based on patterns in said sequence.

Claim 34

The method according to claim 29, further comprising decreasing the magnitude of said current step value based on patterns of said sequence.