EP0484946A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Decoder for SB6B code

Assignee: Fujitsu Ltd

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Filing: 1991-11-07

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Granted: —

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Expires: 2011-11-07

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Abstract

Abstract A circuit for inversely converting the signal of six bits converted by the 5B6B coding rule conversion method in the digital transmission into the original signal of five bits is described. On the occasion of inversely converting the 6-bit signal to the original 5-bit signal, the mark rate of the 6-bit signal to be converted inversely is detected in accordance with the 5B6B coding rule conversion pattern. In this case, all patterns of six bits are not detected but such six bits are divided (1a, 1b) into the upper three bits and lower three bits and the mark rates of six bits are detected (2) from the patterns of upper three bits and lower three bits. Thereby, a number of detected patterns can be reduced and simplification of circuit structure can also be realized.

Inventors

👤 Hiroyuki c/o Fujitsu Kansai Digital Iwaki
👤 Mitsuhiro c/o Fujitsu Kansai Digital Kawaguchi
👤 Shuji c/o Fujitsu Kansai Digital Miyake
👤 Shuji c/o Fujitsu Kansai Digital Yamamoto

Bibliographic Details

Application Number —

Jurisdiction EP

Data Source google_patents

Last Synchronized 2026-10-27 11:06

CPC Classifications

H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4906; H04L25/4908

Claims Analysis

Total Claims: 3

Claim 1

Independent Claim 200 words

A 5B6B coding rule inverse conversion circuit in a data transmission system utilizing the 5B6B code as a code format on a transmission line, comprising: a first decoder (1a) for generating a signal of eight patterns from the upper three bits in a six bits signal which has been converted by the 5B6B coding rule conversion method; a second decoder (1b) for generating the signal of eight patterns from the lower three bits in the six bits; a mark rate detecting circuit (2) for detecting a mark rate of six bits from the signal of eight patterns outputted from the first and second decoders; a code inverse conversion circuit (3) for executing the inverse conversion of the 5B6B coding rule responsive to the mark rates detected by the mark rate detecting circuit (2) in order to convert the six bits into a signal of five bits; and a select circuit (4) for selecting and outputting only one signal among the signal of five bits inversely converted by the code inverse conversion circuit (3), the signal of upper five bits among the six bits and an error signal, responsive to the mark rate detected by the mark rate detecting circuit (2).

Claim 2

Dependent Claim 116 words

A 5B6B coding rule inverse conversion circuit in a data transmission system utilizing the 5B6B code as a code format on a transmission line, comprising: a first mark rate detecting circuit (51) for detecting a mark rate of upper three bits in a six bits signal which has been converted by the 5B6B coding rule conversion method; a second mark rate detecting circuit (52) for detecting the mark rate of lower three bits for the six bits; and a 6-bit mark rate deciding circuit (53) for deciding the mark rate of the six bits, responsive to the mark rate detected by the first mark rate detecting circuit (51) and the second mark rate detecting circuit (52).

Claim 3

Dependent Claim 180 words

A 5B6B coding rule inverse conversion circuit in a data transmission system utilizing the 5B6B code as a code format on a transmission line, comprising: a first half-adder (71) for detecting a mark rate of upper two bits in a six bits signal which has been converted by the 5B6B coding rule conversion method; a second half-adder (72) for detecting the mark rate of intermediate two bits of the six bits; a third half-adder (73) for detecting the mark rate of lower two bits for the six bits; a first decoder (81) for generating a logical signal of eight patterns from the logical signal of upper bits among a 2-bit logical signal indicating the mark rate detected by each half-adder; a second decoder (82) for generating the logical signal of eight patterns from the logical signal of lower bits among the 2-bit logical signal indicating the mark rate; and a 6-bit mark rate deciding circuit (91) for deciding mark rates of the six bits, responsive to a total of 16 patterns generated by the first and second decoders (81, 82).

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